45                     SmallVectorImpl<MCFixup> &Fixups,  in getDirectBrEncoding()  argument
50     return getMachineOpValue(MI, MO, Fixups, STI);  in getDirectBrEncoding()
53   Fixups.push_back(MCFixup::create(0, MO.getExpr(),  in getDirectBrEncoding()
155                                      SmallVectorImpl<MCFixup> &Fixups,  in getCondBrEncoding()  argument
158   if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI);  in getCondBrEncoding()
161   Fixups.push_back(MCFixup::create(0, MO.getExpr(),  in getCondBrEncoding()
168                        SmallVectorImpl<MCFixup> &Fixups,  in getAbsDirectBrEncoding()  argument
171   if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI);  in getAbsDirectBrEncoding()
174   Fixups.push_back(MCFixup::create(0, MO.getExpr(),  in getAbsDirectBrEncoding()
181                      SmallVectorImpl<MCFixup> &Fixups,  in getAbsCondBrEncoding()  argument
184   if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI);  in getAbsCondBrEncoding()
187   Fixups.push_back(MCFixup::create(0, MO.getExpr(),  in getAbsCondBrEncoding()
194                                       SmallVectorImpl<MCFixup> &Fixups,  in getVSRpEvenEncoding()  argument
197   unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI)  in getVSRpEvenEncoding()
203                                        SmallVectorImpl<MCFixup> &Fixups,  in getImm16Encoding()  argument
206   if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI);  in getImm16Encoding()
209   Fixups.push_back(MCFixup::create(IsLittleEndian? 0 : 2, MO.getExpr(),  in getImm16Encoding()
215                                             SmallVectorImpl<MCFixup> &Fixups,  in getImm34Encoding()  argument
221     return getMachineOpValue(MI, MO, Fixups, STI);  in getImm34Encoding()
224   Fixups.push_back(MCFixup::create(0, MO.getExpr(), Fixup));  in getImm34Encoding()
230                                           SmallVectorImpl<MCFixup> &Fixups,  in getImm34EncodingNoPCRel()  argument
232   return getImm34Encoding(MI, OpNo, Fixups, STI,  in getImm34EncodingNoPCRel()
238                                         SmallVectorImpl<MCFixup> &Fixups,  in getImm34EncodingPCRel()  argument
240   return getImm34Encoding(MI, OpNo, Fixups, STI,  in getImm34EncodingPCRel()
245                                              SmallVectorImpl<MCFixup> &Fixups,  in getDispRIEncoding()  argument
249     return getMachineOpValue(MI, MO, Fixups, STI) & 0xFFFF;  in getDispRIEncoding()
252   Fixups.push_back(MCFixup::create(IsLittleEndian? 0 : 2, MO.getExpr(),  in getDispRIEncoding()
259                                      SmallVectorImpl<MCFixup> &Fixups,  in getDispRIXEncoding()  argument
263     return ((getMachineOpValue(MI, MO, Fixups, STI) >> 2) & 0x3FFF);  in getDispRIXEncoding()
266   Fixups.push_back(MCFixup::create(IsLittleEndian? 0 : 2, MO.getExpr(),  in getDispRIXEncoding()
273                                        SmallVectorImpl<MCFixup> &Fixups,  in getDispRIX16Encoding()  argument
279     return ((getMachineOpValue(MI, MO, Fixups, STI) >> 4) & 0xFFF);  in getDispRIX16Encoding()
283   Fixups.push_back(MCFixup::create(IsLittleEndian ? 0 : 2, MO.getExpr(),  in getDispRIX16Encoding()
290                                         SmallVectorImpl<MCFixup> &Fixups,  in getDispRIHashEncoding()  argument
305                                            SmallVectorImpl<MCFixup> &Fixups,  in getDispRI34PCRelEncoding()  argument
319     return (getMachineOpValue(MI, MO, Fixups, STI)) & 0x3FFFFFFFFUL;  in getDispRI34PCRelEncoding()
342     Fixups.push_back(  in getDispRI34PCRelEncoding()
376     Fixups.push_back(  in getDispRI34PCRelEncoding()
388                                       SmallVectorImpl<MCFixup> &Fixups,  in getDispRI34Encoding()  argument
392   return (getMachineOpValue(MI, MO, Fixups, STI)) & 0x3FFFFFFFFUL;  in getDispRI34Encoding()
397                                       SmallVectorImpl<MCFixup> &Fixups,  in getDispSPE8Encoding()  argument
402   return getMachineOpValue(MI, MO, Fixups, STI) >> 3;  in getDispSPE8Encoding()
407                                       SmallVectorImpl<MCFixup> &Fixups,  in getDispSPE4Encoding()  argument
412   return getMachineOpValue(MI, MO, Fixups, STI) >> 2;  in getDispSPE4Encoding()
417                                       SmallVectorImpl<MCFixup> &Fixups,  in getDispSPE2Encoding()  argument
422   return getMachineOpValue(MI, MO, Fixups, STI) >> 1;  in getDispSPE2Encoding()
426                                        SmallVectorImpl<MCFixup> &Fixups,  in getTLSRegEncoding()  argument
429   if (MO.isReg()) return getMachineOpValue(MI, MO, Fixups, STI);  in getTLSRegEncoding()
438   Fixups.push_back(MCFixup::create(IsPCRel ? 1 : 0, Expr,  in getTLSRegEncoding()
446                                        SmallVectorImpl<MCFixup> &Fixups,  in getTLSCallEncoding()  argument
452   Fixups.push_back(MCFixup::create(0, MO.getExpr(),  in getTLSCallEncoding()
454   return getDirectBrEncoding(MI, OpNo, Fixups, STI);  in getTLSCallEncoding()
459                     SmallVectorImpl<MCFixup> &Fixups,  in get_crbitm_encoding()  argument
484                   SmallVectorImpl<MCFixup> &Fixups,  in getMachineOpValue()  argument
505                                          SmallVectorImpl<MCFixup> &Fixups,  in encodeInstruction()  argument
507   uint64_t Bits = getBinaryCodeForInstr(MI, Fixups, STI);  in encodeInstruction()