Lines Matching refs:I
43 bool select(MachineInstr &I) override;
49 bool selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const;
51 bool selectFPToInt(MachineInstr &I, MachineBasicBlock &MBB,
53 bool selectIntToFP(MachineInstr &I, MachineBasicBlock &MBB,
56 bool selectZExt(MachineInstr &I, MachineBasicBlock &MBB,
58 bool selectConstantPool(MachineInstr &I, MachineBasicBlock &MBB,
61 std::optional<bool> selectI64ImmDirect(MachineInstr &I,
65 bool selectI64Imm(MachineInstr &I, MachineBasicBlock &MBB,
130 static bool selectCopy(MachineInstr &I, const TargetInstrInfo &TII, in selectCopy() argument
133 Register DstReg = I.getOperand(0).getReg(); in selectCopy()
146 LLVM_DEBUG(dbgs() << "Failed to constrain " << TII.getName(I.getOpcode()) in selectCopy()
184 bool PPCInstructionSelector::selectIntToFP(MachineInstr &I, in selectIntToFP() argument
190 const DebugLoc &DbgLoc = I.getDebugLoc(); in selectIntToFP()
191 const Register DstReg = I.getOperand(0).getReg(); in selectIntToFP()
192 const Register SrcReg = I.getOperand(1).getReg(); in selectIntToFP()
197 BuildMI(MBB, I, DbgLoc, TII.get(PPC::MTVSRD), MoveReg).addReg(SrcReg); in selectIntToFP()
200 bool IsSigned = I.getOpcode() == TargetOpcode::G_SITOFP; in selectIntToFP()
205 BuildMI(MBB, I, DbgLoc, TII.get(ConvOp), DstReg).addReg(MoveReg); in selectIntToFP()
207 I.eraseFromParent(); in selectIntToFP()
211 bool PPCInstructionSelector::selectFPToInt(MachineInstr &I, in selectFPToInt() argument
217 const DebugLoc &DbgLoc = I.getDebugLoc(); in selectFPToInt()
218 const Register DstReg = I.getOperand(0).getReg(); in selectFPToInt()
219 const Register SrcReg = I.getOperand(1).getReg(); in selectFPToInt()
222 BuildMI(MBB, I, DbgLoc, TII.get(TargetOpcode::COPY), CopyReg).addReg(SrcReg); in selectFPToInt()
226 bool IsSigned = I.getOpcode() == TargetOpcode::G_FPTOSI; in selectFPToInt()
232 BuildMI(MBB, I, DbgLoc, TII.get(ConvOp), ConvReg).addReg(CopyReg); in selectFPToInt()
235 BuildMI(MBB, I, DbgLoc, TII.get(PPC::MFVSRD), DstReg).addReg(ConvReg); in selectFPToInt()
237 I.eraseFromParent(); in selectFPToInt()
241 bool PPCInstructionSelector::selectZExt(MachineInstr &I, MachineBasicBlock &MBB, in selectZExt() argument
243 const Register DstReg = I.getOperand(0).getReg(); in selectZExt()
247 const Register SrcReg = I.getOperand(1).getReg(); in selectZExt()
254 BuildMI(MBB, I, I.getDebugLoc(), TII.get(TargetOpcode::IMPLICIT_DEF), in selectZExt()
259 BuildMI(MBB, I, I.getDebugLoc(), TII.get(TargetOpcode::INSERT_SUBREG), in selectZExt()
266 BuildMI(MBB, I, I.getDebugLoc(), TII.get(PPC::RLDICL), DstReg) in selectZExt()
271 I.eraseFromParent(); in selectZExt()
287 std::optional<bool> PPCInstructionSelector::selectI64ImmDirect(MachineInstr &I, in selectI64ImmDirect() argument
305 return BuildMI(MBB, I, I.getDebugLoc(), TII.get(PPC::LI8), Reg) in selectI64ImmDirect()
311 return BuildMI(MBB, I, I.getDebugLoc(), TII.get(PPC::LIS8), Reg) in selectI64ImmDirect()
326 if (!BuildMI(MBB, I, I.getDebugLoc(), TII.get(Opcode), TmpReg) in selectI64ImmDirect()
330 return BuildMI(MBB, I, I.getDebugLoc(), TII.get(PPC::ORI8), Reg) in selectI64ImmDirect()
343 if (!BuildMI(MBB, I, I.getDebugLoc(), TII.get(PPC::LI8), TmpReg) in selectI64ImmDirect()
347 return BuildMI(MBB, I, I.getDebugLoc(), TII.get(PPC::RLDIC), Reg) in selectI64ImmDirect()
374 if (!BuildMI(MBB, I, I.getDebugLoc(), TII.get(PPC::LI8), TmpReg) in selectI64ImmDirect()
378 return BuildMI(MBB, I, I.getDebugLoc(), TII.get(PPC::RLDICL), Reg) in selectI64ImmDirect()
402 if (!BuildMI(MBB, I, I.getDebugLoc(), TII.get(PPC::LI8), TmpReg) in selectI64ImmDirect()
406 return BuildMI(MBB, I, I.getDebugLoc(), TII.get(PPC::RLDICL), Reg) in selectI64ImmDirect()
418 if (!BuildMI(MBB, I, I.getDebugLoc(), TII.get(PPC::LI8), TmpReg) in selectI64ImmDirect()
422 return BuildMI(MBB, I, I.getDebugLoc(), TII.get(PPC::ORIS8), Reg) in selectI64ImmDirect()
449 if (!BuildMI(MBB, I, I.getDebugLoc(), TII.get(PPC::LI8), TmpReg) in selectI64ImmDirect()
453 return BuildMI(MBB, I, I.getDebugLoc(), TII.get(PPC::RLDICL), Reg) in selectI64ImmDirect()
474 if (!BuildMI(MBB, I, I.getDebugLoc(), TII.get(Opcode), TmpReg) in selectI64ImmDirect()
478 if (!BuildMI(MBB, I, I.getDebugLoc(), TII.get(PPC::ORI8), Tmp2Reg) in selectI64ImmDirect()
483 return BuildMI(MBB, I, I.getDebugLoc(), TII.get(PPC::RLDIC), Reg) in selectI64ImmDirect()
501 if (!BuildMI(MBB, I, I.getDebugLoc(), TII.get(PPC::LIS8), TmpReg) in selectI64ImmDirect()
505 if (!BuildMI(MBB, I, I.getDebugLoc(), TII.get(PPC::ORI8), Tmp2Reg) in selectI64ImmDirect()
510 return BuildMI(MBB, I, I.getDebugLoc(), TII.get(PPC::RLDICL), Reg) in selectI64ImmDirect()
525 if (!BuildMI(MBB, I, I.getDebugLoc(), TII.get(PPC::LIS8), TmpReg) in selectI64ImmDirect()
529 if (!BuildMI(MBB, I, I.getDebugLoc(), TII.get(PPC::ORI8), Tmp2Reg) in selectI64ImmDirect()
534 return BuildMI(MBB, I, I.getDebugLoc(), TII.get(PPC::RLDICL), Reg) in selectI64ImmDirect()
547 if (!BuildMI(MBB, I, I.getDebugLoc(), TII.get(Opcode), TmpReg) in selectI64ImmDirect()
551 if (!BuildMI(MBB, I, I.getDebugLoc(), TII.get(PPC::ORI8), Tmp2Reg) in selectI64ImmDirect()
556 return BuildMI(MBB, I, I.getDebugLoc(), TII.get(PPC::RLDIMI), Reg) in selectI64ImmDirect()
577 if (!BuildMI(MBB, I, I.getDebugLoc(), TII.get(Opcode), TmpReg) in selectI64ImmDirect()
581 if (!BuildMI(MBB, I, I.getDebugLoc(), TII.get(PPC::ORI8), Tmp2Reg) in selectI64ImmDirect()
586 return BuildMI(MBB, I, I.getDebugLoc(), TII.get(PPC::RLDICL), Reg) in selectI64ImmDirect()
599 bool PPCInstructionSelector::selectI64Imm(MachineInstr &I, in selectI64Imm() argument
602 assert(I.getOpcode() == TargetOpcode::G_CONSTANT && "Unexpected G code"); in selectI64Imm()
604 Register DstReg = I.getOperand(0).getReg(); in selectI64Imm()
605 int64_t Imm = I.getOperand(1).getCImm()->getValue().getZExtValue(); in selectI64Imm()
608 if (std::optional<bool> Res = selectI64ImmDirect(I, MBB, MRI, DstReg, Imm)) { in selectI64Imm()
609 I.eraseFromParent(); in selectI64Imm()
622 selectI64ImmDirect(I, MBB, MRI, Reg, Imm & 0xffffffff00000000); in selectI64Imm()
630 if (!BuildMI(MBB, I, I.getDebugLoc(), TII.get(PPC::ORIS8), TmpReg) in selectI64Imm()
638 if (!BuildMI(MBB, I, I.getDebugLoc(), TII.get(PPC::ORI8), DstReg) in selectI64Imm()
644 I.eraseFromParent(); in selectI64Imm()
649 MachineInstr &I, MachineBasicBlock &MBB, MachineRegisterInfo &MRI) const { in selectConstantPool() argument
650 const DebugLoc &DbgLoc = I.getDebugLoc(); in selectConstantPool()
662 const Register DstReg = I.getOperand(0).getReg(); in selectConstantPool()
663 unsigned CPI = I.getOperand(1).getIndex(); in selectConstantPool()
681 MI = BuildMI(MBB, I, DbgLoc, TII.get(PPC::LDtocCPT), DstReg) in selectConstantPool()
687 BuildMI(MBB, I, DbgLoc, TII.get(PPC::ADDIStocHA8), HaAddrReg) in selectConstantPool()
693 MI = BuildMI(MBB, I, DbgLoc, TII.get(PPC::LDtocL), DstReg) in selectConstantPool()
699 MI = BuildMI(MBB, I, DbgLoc, TII.get(PPC::ADDItocL), DstReg) in selectConstantPool()
704 I.eraseFromParent(); in selectConstantPool()
708 bool PPCInstructionSelector::select(MachineInstr &I) { in select() argument
709 auto &MBB = *I.getParent(); in select()
713 if (!isPreISelGenericOpcode(I.getOpcode())) { in select()
714 if (I.isCopy()) in select()
715 return selectCopy(I, TII, MRI, TRI, RBI); in select()
720 if (selectImpl(I, *CoverageInfo)) in select()
723 unsigned Opcode = I.getOpcode(); in select()
730 GLoadStore &LdSt = cast<GLoadStore>(I); in select()
741 I.getOpcode(), RBI.getRegBank(LdSt.getReg(0), MRI, TRI)->getID(), in select()
744 if (NewOpc == I.getOpcode()) in select()
749 I.setDesc(TII.get(NewOpc)); in select()
750 Register AddrReg = I.getOperand(1).getReg(); in select()
751 bool IsKill = I.getOperand(1).isKill(); in select()
752 I.getOperand(1).ChangeToImmediate(0); in select()
753 I.addOperand(*I.getParent()->getParent(), in select()
756 return &I; in select()
767 return selectIntToFP(I, MBB, MRI); in select()
770 return selectFPToInt(I, MBB, MRI); in select()
773 return selectZExt(I, MBB, MRI); in select()
775 return selectI64Imm(I, MBB, MRI); in select()
777 return selectConstantPool(I, MBB, MRI); in select()