Lines Matching refs:Opc
47 unsigned Opc = MI.getOpcode(); in isLoadFromStackSlot() local
49 if ((Opc == Mips::LW) || (Opc == Mips::LD) || in isLoadFromStackSlot()
50 (Opc == Mips::LWC1) || (Opc == Mips::LDC1) || (Opc == Mips::LDC164)) { in isLoadFromStackSlot()
69 unsigned Opc = MI.getOpcode(); in isStoreToStackSlot() local
71 if ((Opc == Mips::SW) || (Opc == Mips::SD) || in isStoreToStackSlot()
72 (Opc == Mips::SWC1) || (Opc == Mips::SDC1) || (Opc == Mips::SDC164)) { in isStoreToStackSlot()
87 unsigned Opc = 0, ZeroReg = 0; in copyPhysReg() local
93 Opc = Mips::MOVE16_MM; in copyPhysReg()
95 Opc = Mips::OR, ZeroReg = Mips::ZERO; in copyPhysReg()
97 Opc = Mips::CFC1; in copyPhysReg()
99 Opc = Mips::MFC1; in copyPhysReg()
101 Opc = isMicroMips ? Mips::MFHI16_MM : Mips::MFHI; in copyPhysReg()
104 Opc = isMicroMips ? Mips::MFLO16_MM : Mips::MFLO; in copyPhysReg()
107 Opc = Mips::MFHI_DSP; in copyPhysReg()
109 Opc = Mips::MFLO_DSP; in copyPhysReg()
116 Opc = Mips::CFCMSA; in copyPhysReg()
120 Opc = Mips::CTC1; in copyPhysReg()
122 Opc = Mips::MTC1; in copyPhysReg()
124 Opc = Mips::MTHI, DestReg = 0; in copyPhysReg()
126 Opc = Mips::MTLO, DestReg = 0; in copyPhysReg()
128 Opc = Mips::MTHI_DSP; in copyPhysReg()
130 Opc = Mips::MTLO_DSP; in copyPhysReg()
144 Opc = Mips::FMOV_S; in copyPhysReg()
146 Opc = Mips::FMOV_D32; in copyPhysReg()
148 Opc = Mips::FMOV_D64; in copyPhysReg()
151 Opc = Mips::OR64, ZeroReg = Mips::ZERO_64; in copyPhysReg()
153 Opc = Mips::MFHI64, SrcReg = 0; in copyPhysReg()
155 Opc = Mips::MFLO64, SrcReg = 0; in copyPhysReg()
157 Opc = Mips::DMFC1; in copyPhysReg()
161 Opc = Mips::MTHI64, DestReg = 0; in copyPhysReg()
163 Opc = Mips::MTLO64, DestReg = 0; in copyPhysReg()
165 Opc = Mips::DMTC1; in copyPhysReg()
169 Opc = Mips::MOVE_V; in copyPhysReg()
172 assert(Opc && "Cannot copy registers"); in copyPhysReg()
174 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc)); in copyPhysReg()
222 unsigned Opc = 0; in storeRegToStack() local
225 Opc = Mips::SW; in storeRegToStack()
227 Opc = Mips::SD; in storeRegToStack()
229 Opc = Mips::STORE_ACC64; in storeRegToStack()
231 Opc = Mips::STORE_ACC64DSP; in storeRegToStack()
233 Opc = Mips::STORE_ACC128; in storeRegToStack()
235 Opc = Mips::STORE_CCOND_DSP; in storeRegToStack()
237 Opc = Mips::SWC1; in storeRegToStack()
239 Opc = Mips::SDC1; in storeRegToStack()
241 Opc = Mips::SDC164; in storeRegToStack()
243 Opc = Mips::ST_B; in storeRegToStack()
246 Opc = Mips::ST_H; in storeRegToStack()
249 Opc = Mips::ST_W; in storeRegToStack()
252 Opc = Mips::ST_D; in storeRegToStack()
254 Opc = Mips::SW; in storeRegToStack()
256 Opc = Mips::SD; in storeRegToStack()
258 Opc = Mips::SW; in storeRegToStack()
260 Opc = Mips::SD; in storeRegToStack()
262 Opc = Mips::SWDSP; in storeRegToStack()
283 assert(Opc && "Register class not handled!"); in storeRegToStack()
284 BuildMI(MBB, I, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill)) in storeRegToStack()
295 unsigned Opc = 0; in loadRegFromStack() local
303 Opc = Mips::LW; in loadRegFromStack()
305 Opc = Mips::LD; in loadRegFromStack()
307 Opc = Mips::LOAD_ACC64; in loadRegFromStack()
309 Opc = Mips::LOAD_ACC64DSP; in loadRegFromStack()
311 Opc = Mips::LOAD_ACC128; in loadRegFromStack()
313 Opc = Mips::LOAD_CCOND_DSP; in loadRegFromStack()
315 Opc = Mips::LWC1; in loadRegFromStack()
317 Opc = Mips::LDC1; in loadRegFromStack()
319 Opc = Mips::LDC164; in loadRegFromStack()
321 Opc = Mips::LD_B; in loadRegFromStack()
324 Opc = Mips::LD_H; in loadRegFromStack()
327 Opc = Mips::LD_W; in loadRegFromStack()
330 Opc = Mips::LD_D; in loadRegFromStack()
332 Opc = Mips::LW; in loadRegFromStack()
334 Opc = Mips::LD; in loadRegFromStack()
336 Opc = Mips::LW; in loadRegFromStack()
338 Opc = Mips::LD; in loadRegFromStack()
340 Opc = Mips::LWDSP; in loadRegFromStack()
342 assert(Opc && "Register class not handled!"); in loadRegFromStack()
345 BuildMI(MBB, I, DL, get(Opc), DestReg) in loadRegFromStack()
365 BuildMI(MBB, I, DL, get(Opc), Reg) in loadRegFromStack()
376 unsigned Opc; in expandPostRAPseudo() local
421 Opc = isMicroMips ? Mips::CVT_D32_W_MM : Mips::CVT_D32_W; in expandPostRAPseudo()
422 expandCvtFPInt(MBB, MI, Opc, Mips::MTC1, false); in expandPostRAPseudo()
428 Opc = isMicroMips ? Mips::CVT_D64_W_MM : Mips::CVT_D64_W; in expandPostRAPseudo()
429 expandCvtFPInt(MBB, MI, Opc, Mips::MTC1, true); in expandPostRAPseudo()
458 bool MipsSEInstrInfo::isBranchWithImm(unsigned Opc) const { in isBranchWithImm()
459 switch (Opc) { in isBranchWithImm()
472 unsigned MipsSEInstrInfo::getOppositeBranchOpc(unsigned Opc) const { in getOppositeBranchOpc()
473 switch (Opc) { in getOppositeBranchOpc()
575 unsigned Opc = ABI.GetPtrAdduOp(); in adjustStackPtr() local
577 Opc = ABI.GetPtrSubuOp(); in adjustStackPtr()
581 BuildMI(MBB, I, DL, get(Opc), SP).addReg(SP).addReg(Reg, RegState::Kill); in adjustStackPtr()
612 if (Inst->Opc == LUi) in loadImmediate()
615 BuildMI(MBB, II, DL, get(Inst->Opc), Reg).addReg(ZEROReg) in loadImmediate()
620 BuildMI(MBB, II, DL, get(Inst->Opc), Reg).addReg(Reg, RegState::Kill) in loadImmediate()
629 unsigned MipsSEInstrInfo::getAnalyzableBrOpc(unsigned Opc) const { in getAnalyzableBrOpc()
630 return (Opc == Mips::BEQ || Opc == Mips::BEQ_MM || Opc == Mips::BNE || in getAnalyzableBrOpc()
631 Opc == Mips::BNE_MM || Opc == Mips::BGTZ || Opc == Mips::BGEZ || in getAnalyzableBrOpc()
632 Opc == Mips::BLTZ || Opc == Mips::BLEZ || Opc == Mips::BEQ64 || in getAnalyzableBrOpc()
633 Opc == Mips::BNE64 || Opc == Mips::BGTZ64 || Opc == Mips::BGEZ64 || in getAnalyzableBrOpc()
634 Opc == Mips::BLTZ64 || Opc == Mips::BLEZ64 || Opc == Mips::BC1T || in getAnalyzableBrOpc()
635 Opc == Mips::BC1F || Opc == Mips::B || Opc == Mips::J || in getAnalyzableBrOpc()
636 Opc == Mips::J_MM || Opc == Mips::B_MM || Opc == Mips::BEQZC_MM || in getAnalyzableBrOpc()
637 Opc == Mips::BNEZC_MM || Opc == Mips::BEQC || Opc == Mips::BNEC || in getAnalyzableBrOpc()
638 Opc == Mips::BLTC || Opc == Mips::BGEC || Opc == Mips::BLTUC || in getAnalyzableBrOpc()
639 Opc == Mips::BGEUC || Opc == Mips::BGTZC || Opc == Mips::BLEZC || in getAnalyzableBrOpc()
640 Opc == Mips::BGEZC || Opc == Mips::BLTZC || Opc == Mips::BEQZC || in getAnalyzableBrOpc()
641 Opc == Mips::BNEZC || Opc == Mips::BEQZC64 || Opc == Mips::BNEZC64 || in getAnalyzableBrOpc()
642 Opc == Mips::BEQC64 || Opc == Mips::BNEC64 || Opc == Mips::BGEC64 || in getAnalyzableBrOpc()
643 Opc == Mips::BGEUC64 || Opc == Mips::BLTC64 || Opc == Mips::BLTUC64 || in getAnalyzableBrOpc()
644 Opc == Mips::BGTZC64 || Opc == Mips::BGEZC64 || in getAnalyzableBrOpc()
645 Opc == Mips::BLTZC64 || Opc == Mips::BLEZC64 || Opc == Mips::BC || in getAnalyzableBrOpc()
646 Opc == Mips::BBIT0 || Opc == Mips::BBIT1 || Opc == Mips::BBIT032 || in getAnalyzableBrOpc()
647 Opc == Mips::BBIT132 || Opc == Mips::BC_MMR6 || in getAnalyzableBrOpc()
648 Opc == Mips::BEQC_MMR6 || Opc == Mips::BNEC_MMR6 || in getAnalyzableBrOpc()
649 Opc == Mips::BLTC_MMR6 || Opc == Mips::BGEC_MMR6 || in getAnalyzableBrOpc()
650 Opc == Mips::BLTUC_MMR6 || Opc == Mips::BGEUC_MMR6 || in getAnalyzableBrOpc()
651 Opc == Mips::BGTZC_MMR6 || Opc == Mips::BLEZC_MMR6 || in getAnalyzableBrOpc()
652 Opc == Mips::BGEZC_MMR6 || Opc == Mips::BLTZC_MMR6 || in getAnalyzableBrOpc()
653 Opc == Mips::BEQZC_MMR6 || Opc == Mips::BNEZC_MMR6) ? Opc : 0; in getAnalyzableBrOpc()
680 MipsSEInstrInfo::compareOpndSize(unsigned Opc, in compareOpndSize() argument
682 const MCInstrDesc &Desc = get(Opc); in compareOpndSize()