Lines Matching refs:I
38 bool select(MachineInstr &I) override;
42 bool selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const;
47 bool selectCopy(MachineInstr &I, MachineRegisterInfo &MRI) const;
50 unsigned selectLoadStoreOpCode(MachineInstr &I,
52 bool buildUnalignedStore(MachineInstr &I, unsigned Opc,
55 bool buildUnalignedLoad(MachineInstr &I, unsigned Opc, Register Dest,
105 bool MipsInstructionSelector::selectCopy(MachineInstr &I, in selectCopy() argument
107 Register DstReg = I.getOperand(0).getReg(); in selectCopy()
113 LLVM_DEBUG(dbgs() << "Failed to constrain " << TII.getName(I.getOpcode()) in selectCopy()
182 MipsInstructionSelector::selectLoadStoreOpCode(MachineInstr &I, in selectLoadStoreOpCode() argument
184 const Register ValueReg = I.getOperand(0).getReg(); in selectLoadStoreOpCode()
187 const unsigned MemSizeInBytes = (*I.memoperands_begin())->getSize(); in selectLoadStoreOpCode()
188 unsigned Opc = I.getOpcode(); in selectLoadStoreOpCode()
258 MachineInstr &I, unsigned Opc, MachineOperand &BaseAddr, unsigned Offset, in buildUnalignedStore() argument
261 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(Opc)) in buildUnalignedStore()
262 .add(I.getOperand(0)) in buildUnalignedStore()
272 MachineInstr &I, unsigned Opc, Register Dest, MachineOperand &BaseAddr, in buildUnalignedLoad() argument
275 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(Opc)) in buildUnalignedLoad()
280 .addMemOperand(*I.memoperands_begin()); in buildUnalignedLoad()
286 bool MipsInstructionSelector::select(MachineInstr &I) { in select() argument
288 MachineBasicBlock &MBB = *I.getParent(); in select()
292 if (!isPreISelGenericOpcode(I.getOpcode())) { in select()
293 if (I.isCopy()) in select()
294 return selectCopy(I, MRI); in select()
299 if (I.getOpcode() == Mips::G_MUL && in select()
300 isRegInGprb(I.getOperand(0).getReg(), MRI)) { in select()
301 MachineInstr *Mul = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::MUL)) in select()
302 .add(I.getOperand(0)) in select()
303 .add(I.getOperand(1)) in select()
304 .add(I.getOperand(2)); in select()
310 I.eraseFromParent(); in select()
314 if (selectImpl(I, *CoverageInfo)) in select()
320 switch (I.getOpcode()) { in select()
325 PseudoMULTu = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::PseudoMULTu)) in select()
327 .add(I.getOperand(1)) in select()
328 .add(I.getOperand(2)); in select()
332 PseudoMove = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::PseudoMFHI)) in select()
333 .addDef(I.getOperand(0).getReg()) in select()
338 I.eraseFromParent(); in select()
342 MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::ADDu)) in select()
343 .add(I.getOperand(0)) in select()
344 .add(I.getOperand(1)) in select()
345 .add(I.getOperand(2)); in select()
350 I.setDesc(TII.get(COPY)); in select()
351 return selectCopy(I, MRI); in select()
354 MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::ADDiu)) in select()
355 .add(I.getOperand(0)) in select()
356 .add(I.getOperand(1)) in select()
361 MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::BNE)) in select()
362 .add(I.getOperand(0)) in select()
364 .add(I.getOperand(1)); in select()
374 MachineInstr *SLL = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::SLL)) in select()
376 .addUse(I.getOperand(2).getReg()) in select()
382 MachineInstr *ADDu = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::ADDu)) in select()
384 .addUse(I.getOperand(0).getReg()) in select()
391 BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::LW)) in select()
394 .addJumpTableIndex(I.getOperand(1).getIndex(), MipsII::MO_ABS_LO) in select()
403 MachineInstr *ADDu = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::ADDu)) in select()
413 BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::PseudoIndirectBranch)) in select()
418 I.eraseFromParent(); in select()
422 MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::PseudoIndirectBranch)) in select()
423 .add(I.getOperand(0)); in select()
427 const Register DestReg = I.getOperand(0).getReg(); in select()
435 I.setDesc(TII.get(TargetOpcode::PHI)); in select()
442 auto MMO = *I.memoperands_begin(); in select()
443 MachineOperand BaseAddr = I.getOperand(1); in select()
452 MachineInstr *Addr = MRI.getVRegDef(I.getOperand(1).getReg()); in select()
467 if (MMO->getSize() != 4 || !isRegInGprb(I.getOperand(0).getReg(), MRI)) in select()
470 if (I.getOpcode() == G_STORE) { in select()
471 if (!buildUnalignedStore(I, Mips::SWL, BaseAddr, SignedOffset + 3, MMO)) in select()
473 if (!buildUnalignedStore(I, Mips::SWR, BaseAddr, SignedOffset, MMO)) in select()
475 I.eraseFromParent(); in select()
479 if (I.getOpcode() == G_LOAD) { in select()
481 BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::IMPLICIT_DEF)) in select()
484 if (!buildUnalignedLoad(I, Mips::LWL, Tmp, BaseAddr, SignedOffset + 3, in select()
487 if (!buildUnalignedLoad(I, Mips::LWR, I.getOperand(0).getReg(), in select()
490 I.eraseFromParent(); in select()
497 const unsigned NewOpc = selectLoadStoreOpCode(I, MRI); in select()
498 if (NewOpc == I.getOpcode()) in select()
501 MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(NewOpc)) in select()
502 .add(I.getOperand(0)) in select()
513 bool IsSigned = I.getOpcode() == G_SREM || I.getOpcode() == G_SDIV; in select()
514 bool IsDiv = I.getOpcode() == G_UDIV || I.getOpcode() == G_SDIV; in select()
517 PseudoDIV = BuildMI(MBB, I, I.getDebugLoc(), in select()
520 .add(I.getOperand(1)) in select()
521 .add(I.getOperand(2)); in select()
525 PseudoMove = BuildMI(MBB, I, I.getDebugLoc(), in select()
527 .addDef(I.getOperand(0).getReg()) in select()
532 I.eraseFromParent(); in select()
537 MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::MOVN_I_I)) in select()
538 .add(I.getOperand(0)) in select()
539 .add(I.getOperand(2)) in select()
540 .add(I.getOperand(1)) in select()
541 .add(I.getOperand(3)); in select()
545 if (I.getNumOperands() != 3) in select()
547 Register Src = I.getOperand(2).getReg(); in select()
548 Register Lo = I.getOperand(0).getReg(); in select()
549 Register Hi = I.getOperand(1).getReg(); in select()
557 MachineInstr *ExtractLo = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Opcode)) in select()
564 MachineInstr *ExtractHi = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Opcode)) in select()
571 I.eraseFromParent(); in select()
575 Register Dst = I.getOperand(0).getReg(); in select()
576 MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::IMPLICIT_DEF)) in select()
584 MachineIRBuilder B(I); in select()
585 if (!materialize32BitImm(I.getOperand(0).getReg(), in select()
586 I.getOperand(1).getCImm()->getValue(), B)) in select()
589 I.eraseFromParent(); in select()
593 const APFloat &FPimm = I.getOperand(1).getFPImm()->getValueAPF(); in select()
595 unsigned Size = MRI.getType(I.getOperand(0).getReg()).getSizeInBits(); in select()
599 MachineIRBuilder B(I); in select()
604 B.buildInstr(Mips::MTC1, {I.getOperand(0).getReg()}, {GPRReg}); in select()
611 MachineIRBuilder B(I); in select()
619 {I.getOperand(0).getReg()}, {GPRRegLow, GPRRegHigh}); in select()
624 I.eraseFromParent(); in select()
628 unsigned Size = MRI.getType(I.getOperand(0).getReg()).getSizeInBits(); in select()
632 MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(FABSOpcode)) in select()
633 .add(I.getOperand(0)) in select()
634 .add(I.getOperand(1)); in select()
638 unsigned FromSize = MRI.getType(I.getOperand(1).getReg()).getSizeInBits(); in select()
639 unsigned ToSize = MRI.getType(I.getOperand(0).getReg()).getSizeInBits(); in select()
651 MachineInstr *Trunc = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Opcode)) in select()
653 .addUse(I.getOperand(1).getReg()); in select()
657 MachineInstr *Move = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::MFC1)) in select()
658 .addDef(I.getOperand(0).getReg()) in select()
663 I.eraseFromParent(); in select()
667 const llvm::GlobalValue *GVal = I.getOperand(1).getGlobal(); in select()
669 MachineInstr *LWGOT = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::LW)) in select()
670 .addDef(I.getOperand(0).getReg()) in select()
678 if (I.getOperand(1).getTargetFlags() == MipsII::MO_GOT_CALL) in select()
693 BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::ADDiu)) in select()
694 .addDef(I.getOperand(0).getReg()) in select()
704 MachineInstr *LUi = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::LUi)) in select()
712 BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::ADDiu)) in select()
713 .addDef(I.getOperand(0).getReg()) in select()
720 I.eraseFromParent(); in select()
725 MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::LW)) in select()
726 .addDef(I.getOperand(0).getReg()) in select()
729 .addJumpTableIndex(I.getOperand(1).getIndex(), MipsII::MO_GOT) in select()
735 BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::LUi)) in select()
736 .addDef(I.getOperand(0).getReg()) in select()
737 .addJumpTableIndex(I.getOperand(1).getIndex(), MipsII::MO_ABS_HI); in select()
756 Register ICMPReg = I.getOperand(0).getReg(); in select()
758 Register LHS = I.getOperand(2).getReg(); in select()
759 Register RHS = I.getOperand(3).getReg(); in select()
761 static_cast<CmpInst::Predicate>(I.getOperand(1).getPredicate()); in select()
804 MachineIRBuilder B(I); in select()
818 I.eraseFromParent(); in select()
825 I.getOperand(1).getPredicate())) { in select()
872 BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::ADDiu)) in select()
877 unsigned Size = MRI.getType(I.getOperand(2).getReg()).getSizeInBits(); in select()
881 MachineInstr *FCMP = BuildMI(MBB, I, I.getDebugLoc(), TII.get(FCMPOpcode)) in select()
882 .addUse(I.getOperand(2).getReg()) in select()
883 .addUse(I.getOperand(3).getReg()) in select()
888 MachineInstr *Move = BuildMI(MBB, I, I.getDebugLoc(), TII.get(MoveOpcode)) in select()
889 .addDef(I.getOperand(0).getReg()) in select()
896 I.eraseFromParent(); in select()
900 MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::SYNC)).addImm(0); in select()
909 BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::LEA_ADDiu)) in select()
916 MachineInstr *Store = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::SW)) in select()
918 .addUse(I.getOperand(0).getReg()) in select()
923 I.eraseFromParent(); in select()
930 I.eraseFromParent(); in select()