324   Register ResultReg = createResultReg(&Mips::GPR32RegClass);  in emitLogicalOp()
340     Register ResultReg = createResultReg(&Mips::GPR32RegClass);  in fastMaterializeAlloca()
354   const TargetRegisterClass *RC = &Mips::GPR32RegClass;  in materializeInt()
391     unsigned TempReg = materialize32BitInt(Imm, &Mips::GPR32RegClass);  in materializeFP()
397     unsigned TempReg1 = materialize32BitInt(Imm >> 32, &Mips::GPR32RegClass);  in materializeFP()
399         materialize32BitInt(Imm & 0xFFFFFFFF, &Mips::GPR32RegClass);  in materializeFP()
410   const TargetRegisterClass *RC = &Mips::GPR32RegClass;  in materializeGV()
432   const TargetRegisterClass *RC = &Mips::GPR32RegClass;  in materializeExternalCallSym()
648     Register TempReg = createResultReg(&Mips::GPR32RegClass);  in emitCmp()
654     Register TempReg = createResultReg(&Mips::GPR32RegClass);  in emitCmp()
666     Register TempReg = createResultReg(&Mips::GPR32RegClass);  in emitCmp()
672     Register TempReg = createResultReg(&Mips::GPR32RegClass);  in emitCmp()
684     Register TempReg = createResultReg(&Mips::GPR32RegClass);  in emitCmp()
690     Register TempReg = createResultReg(&Mips::GPR32RegClass);  in emitCmp()
736     Register RegWithZero = createResultReg(&Mips::GPR32RegClass);  in emitCmp()
737     Register RegWithOne = createResultReg(&Mips::GPR32RegClass);  in emitCmp()
759     ResultReg = createResultReg(&Mips::GPR32RegClass);  in emitLoad()
763     ResultReg = createResultReg(&Mips::GPR32RegClass);  in emitLoad()
767     ResultReg = createResultReg(&Mips::GPR32RegClass);  in emitLoad()
953       ZExtCondReg = createResultReg(&Mips::GPR32RegClass);  in selectBranch()
979   Register ResultReg = createResultReg(&Mips::GPR32RegClass);  in selectCmp()
1026     RC = &Mips::GPR32RegClass;  in selectSelect()
1045   Register ZExtCondReg = createResultReg(&Mips::GPR32RegClass);  in selectSelect()
1118   Register DestReg = createResultReg(&Mips::GPR32RegClass);  in selectFPToInt()
1383       Allocation.emplace_back(&Mips::GPR32RegClass, *NextGPR32++);  in fastLowerArguments()
1403       Allocation.emplace_back(&Mips::GPR32RegClass, *NextGPR32++);  in fastLowerArguments()
1594     Register DestReg = createResultReg(&Mips::GPR32RegClass);  in fastLowerIntrinsicCall()
1605           R = createResultReg(&Mips::GPR32RegClass);  in fastLowerIntrinsicCall()
1618         Register TempReg = createResultReg(&Mips::GPR32RegClass);  in fastLowerIntrinsicCall()
1626           R = createResultReg(&Mips::GPR32RegClass);  in fastLowerIntrinsicCall()
1815   Register ResultReg = createResultReg(&Mips::GPR32RegClass);  in selectIntExt()
1836   Register TempReg = createResultReg(&Mips::GPR32RegClass);  in emitIntSExt32r1()
1904   unsigned DestReg = createResultReg(&Mips::GPR32RegClass);  in emitIntExt()
1940   Register ResultReg = createResultReg(&Mips::GPR32RegClass);  in selectDivRem()
1959   Register ResultReg = createResultReg(&Mips::GPR32RegClass);  in selectShift()
1971     Register TempReg = createResultReg(&Mips::GPR32RegClass);  in selectShift()
2097     Register TempReg = createResultReg(&Mips::GPR32RegClass);  in getRegEnsuringSimpleIntegerWidening()
2108         materialize32BitInt(Addr.getOffset(), &Mips::GPR32RegClass);  in simplifyAddress()
2109     Register DestReg = createResultReg(&Mips::GPR32RegClass);  in simplifyAddress()