119     TmpInst0.setOpcode(Mips::JALR64);  in emitPseudoIndirectBranch()
124       TmpInst0.setOpcode(Mips::JRC16_MMR6);  in emitPseudoIndirectBranch()
126       TmpInst0.setOpcode(Mips::JALR);  in emitPseudoIndirectBranch()
131     TmpInst0.setOpcode(Mips::JR_MM);  in emitPseudoIndirectBranch()
134     TmpInst0.setOpcode(Mips::JR);  in emitPseudoIndirectBranch()
140     unsigned ZeroReg = Subtarget->isGP64bit() ? Mips::ZERO_64 : Mips::ZERO;  in emitPseudoIndirectBranch()
203   if (InConstantPool && Opc != Mips::CONSTPOOL_ENTRY) {  in emitInstruction()
207   if (Opc == Mips::CONSTPOOL_ENTRY) {  in emitInstruction()
235   case Mips::PATCHABLE_FUNCTION_ENTER:  in emitInstruction()
238   case Mips::PATCHABLE_FUNCTION_EXIT:  in emitInstruction()
241   case Mips::PATCHABLE_TAIL_CALL:  in emitInstruction()
263     if (I->getOpcode() == Mips::PseudoReturn ||  in emitInstruction()
264         I->getOpcode() == Mips::PseudoReturn64 ||  in emitInstruction()
265         I->getOpcode() == Mips::PseudoIndirectBranch ||  in emitInstruction()
266         I->getOpcode() == Mips::PseudoIndirectBranch64 ||  in emitInstruction()
267         I->getOpcode() == Mips::TAILCALLREG ||  in emitInstruction()
268         I->getOpcode() == Mips::TAILCALLREG64) {  in emitInstruction()
337   unsigned CPURegSize = TRI->getRegSizeInBits(Mips::GPR32RegClass) / 8;  in printSavedRegsBitmask()
338   unsigned FGR32RegSize = TRI->getRegSizeInBits(Mips::FGR32RegClass) / 8;  in printSavedRegsBitmask()
339   unsigned AFGR64RegSize = TRI->getRegSizeInBits(Mips::AFGR64RegClass) / 8;  in printSavedRegsBitmask()
349     if (Mips::FGR32RegClass.contains(Reg)) {  in printSavedRegsBitmask()
352     } else if (Mips::AFGR64RegClass.contains(Reg)) {  in printSavedRegsBitmask()
356     } else if (Mips::GPR32RegClass.contains(Reg))  in printSavedRegsBitmask()
694   case Mips::SWM32_MM:  in printMemOperand()
695   case Mips::LWM32_MM:  in printMemOperand()
719   O << Mips::MipsFCCToString((Mips::CondCode)MO.getImm());  in printFCCOperand()
821   I.setOpcode(Mips::JAL);  in EmitJal()
844   if (Opcode == Mips::MTC1) {  in EmitInstrRegReg()
884   unsigned MovOpc = ToFP ? Mips::MTC1 : Mips::MFC1;  in EmitSwapFPIntParams()
887     EmitInstrRegReg(STI, MovOpc, Mips::A0, Mips::F12);  in EmitSwapFPIntParams()
890     EmitMovFPIntPair(STI, MovOpc, Mips::A0, Mips::A1, Mips::F12, Mips::F14, LE);  in EmitSwapFPIntParams()
893     EmitInstrRegReg(STI, MovOpc, Mips::A0, Mips::F12);  in EmitSwapFPIntParams()
894     EmitMovFPIntPair(STI, MovOpc, Mips::A2, Mips::A3, Mips::F14, Mips::F15, LE);  in EmitSwapFPIntParams()
897     EmitMovFPIntPair(STI, MovOpc, Mips::A0, Mips::A1, Mips::F12, Mips::F13, LE);  in EmitSwapFPIntParams()
900     EmitMovFPIntPair(STI, MovOpc, Mips::A0, Mips::A1, Mips::F12, Mips::F13, LE);  in EmitSwapFPIntParams()
901     EmitMovFPIntPair(STI, MovOpc, Mips::A2, Mips::A3, Mips::F14, Mips::F15, LE);  in EmitSwapFPIntParams()
904     EmitMovFPIntPair(STI, MovOpc, Mips::A0, Mips::A1, Mips::F12, Mips::F13, LE);  in EmitSwapFPIntParams()
905     EmitInstrRegReg(STI, MovOpc, Mips::A2, Mips::F14);  in EmitSwapFPIntParams()
917   unsigned MovOpc = Mips::MFC1;  in EmitSwapFPIntRetval()
920     EmitInstrRegReg(STI, MovOpc, Mips::V0, Mips::F0);  in EmitSwapFPIntRetval()
923     EmitMovFPIntPair(STI, MovOpc, Mips::V0, Mips::V1, Mips::F0, Mips::F1, LE);  in EmitSwapFPIntRetval()
926     EmitMovFPIntPair(STI, MovOpc, Mips::V0, Mips::V1, Mips::F0, Mips::F1, LE);  in EmitSwapFPIntRetval()
929     EmitMovFPIntPair(STI, MovOpc, Mips::V0, Mips::V1, Mips::F0, Mips::F1, LE);  in EmitSwapFPIntRetval()
930     EmitMovFPIntPair(STI, MovOpc, Mips::A0, Mips::A1, Mips::F2, Mips::F3, LE);  in EmitSwapFPIntRetval()
1059   EmitInstrRegRegReg(*STI, Mips::OR, Mips::S2, Mips::RA, Mips::ZERO);  in EmitFPCallStub()
1074   EmitInstrReg(*STI, Mips::JR, Mips::S2);  in EmitFPCallStub()
1176   EmitToStreamer(*OutStreamer, MCInstBuilder(Mips::BEQ)  in EmitSled()
1177                                    .addReg(Mips::ZERO)  in EmitSled()
1178                                    .addReg(Mips::ZERO)  in EmitSled()
1182     EmitToStreamer(*OutStreamer, MCInstBuilder(Mips::SLL)  in EmitSled()
1183                                      .addReg(Mips::ZERO)  in EmitSled()
1184                                      .addReg(Mips::ZERO)  in EmitSled()
1191                    MCInstBuilder(Mips::ADDiu)  in EmitSled()
1192                        .addReg(Mips::T9)  in EmitSled()
1193                        .addReg(Mips::T9)  in EmitSled()
1260   return (Opcode == Mips::LONG_BRANCH_LUi  in isLongBranchPseudo()
1261           || Opcode == Mips::LONG_BRANCH_LUi2Op  in isLongBranchPseudo()
1262           || Opcode == Mips::LONG_BRANCH_LUi2Op_64  in isLongBranchPseudo()
1263           || Opcode == Mips::LONG_BRANCH_ADDiu  in isLongBranchPseudo()
1264           || Opcode == Mips::LONG_BRANCH_ADDiu2Op  in isLongBranchPseudo()
1265           || Opcode == Mips::LONG_BRANCH_DADDiu  in isLongBranchPseudo()
1266           || Opcode == Mips::LONG_BRANCH_DADDiu2Op);  in isLongBranchPseudo()