Lines Matching refs:Fixups
135 SmallVectorImpl<MCFixup> &Fixups, in encodeInstruction() argument
162 size_t N = Fixups.size(); in encodeInstruction()
163 uint32_t Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI); in encodeInstruction()
188 if (Fixups.size() > N) in encodeInstruction()
189 Fixups.pop_back(); in encodeInstruction()
192 Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI); in encodeInstruction()
197 unsigned RegPair = getMovePRegPairOpValue(MI, 0, Fixups, STI); in encodeInstruction()
226 SmallVectorImpl<MCFixup> &Fixups, in getBranchTargetOpValue() argument
238 Fixups.push_back(MCFixup::create(0, FixupExpression, in getBranchTargetOpValue()
248 SmallVectorImpl<MCFixup> &Fixups, in getBranchTargetOpValue1SImm16() argument
260 Fixups.push_back(MCFixup::create(0, FixupExpression, in getBranchTargetOpValue1SImm16()
270 SmallVectorImpl<MCFixup> &Fixups, in getBranchTargetOpValueMMR6() argument
283 Fixups.push_back(MCFixup::create(0, FixupExpression, in getBranchTargetOpValueMMR6()
293 SmallVectorImpl<MCFixup> &Fixups, in getBranchTargetOpValueLsl2MMR6() argument
306 Fixups.push_back(MCFixup::create(0, FixupExpression, in getBranchTargetOpValueLsl2MMR6()
316 SmallVectorImpl<MCFixup> &Fixups, in getBranchTarget7OpValueMM() argument
327 Fixups.push_back(MCFixup::create(0, Expr, in getBranchTarget7OpValueMM()
337 SmallVectorImpl<MCFixup> &Fixups, in getBranchTargetOpValueMMPC10() argument
348 Fixups.push_back(MCFixup::create(0, Expr, in getBranchTargetOpValueMMPC10()
358 SmallVectorImpl<MCFixup> &Fixups, in getBranchTargetOpValueMM() argument
369 Fixups.push_back(MCFixup::create(0, Expr, in getBranchTargetOpValueMM()
380 SmallVectorImpl<MCFixup> &Fixups, in getBranchTarget21OpValue() argument
392 Fixups.push_back(MCFixup::create(0, FixupExpression, in getBranchTarget21OpValue()
402 SmallVectorImpl<MCFixup> &Fixups, in getBranchTarget21OpValueMM() argument
414 Fixups.push_back(MCFixup::create(0, FixupExpression, in getBranchTarget21OpValueMM()
424 SmallVectorImpl<MCFixup> &Fixups, in getBranchTarget26OpValue() argument
436 Fixups.push_back(MCFixup::create(0, FixupExpression, in getBranchTarget26OpValue()
445 const MCInst &MI, unsigned OpNo, SmallVectorImpl<MCFixup> &Fixups, in getBranchTarget26OpValueMM() argument
458 Fixups.push_back(MCFixup::create(0, FixupExpression, in getBranchTarget26OpValueMM()
468 SmallVectorImpl<MCFixup> &Fixups, in getJumpOffset16OpValue() argument
478 Mips::Fixups FixupKind = in getJumpOffset16OpValue()
480 Fixups.push_back(MCFixup::create(0, Expr, MCFixupKind(FixupKind))); in getJumpOffset16OpValue()
489 SmallVectorImpl<MCFixup> &Fixups, in getJumpTargetOpValue() argument
499 Fixups.push_back(MCFixup::create(0, Expr, in getJumpTargetOpValue()
506 SmallVectorImpl<MCFixup> &Fixups, in getJumpTargetOpValueMM() argument
516 Fixups.push_back(MCFixup::create(0, Expr, in getJumpTargetOpValueMM()
523 SmallVectorImpl<MCFixup> &Fixups, in getUImm5Lsl2Encoding() argument
528 unsigned Res = getMachineOpValue(MI, MO, Fixups, STI); in getUImm5Lsl2Encoding()
541 SmallVectorImpl<MCFixup> &Fixups, in getSImm3Lsa2Value() argument
554 SmallVectorImpl<MCFixup> &Fixups, in getUImm6Lsl2Encoding() argument
567 SmallVectorImpl<MCFixup> &Fixups, in getSImm9AddiuspValue() argument
579 getExprOpValue(const MCExpr *Expr, SmallVectorImpl<MCFixup> &Fixups, in getExprOpValue() argument
593 getExprOpValue(cast<MCBinaryExpr>(Expr)->getLHS(), Fixups, STI); in getExprOpValue()
594 Res += getExprOpValue(cast<MCBinaryExpr>(Expr)->getRHS(), Fixups, STI); in getExprOpValue()
601 Mips::Fixups FixupKind = Mips::Fixups(0); in getExprOpValue()
610 return getExprOpValue(MipsExpr->getSubExpr(), Fixups, STI); in getExprOpValue()
711 Fixups.push_back(MCFixup::create(0, MipsExpr, MCFixupKind(FixupKind))); in getExprOpValue()
724 SmallVectorImpl<MCFixup> &Fixups, in getMachineOpValue() argument
737 return getExprOpValue(MO.getExpr(),Fixups, STI); in getMachineOpValue()
744 SmallVectorImpl<MCFixup> &Fixups, in getMemEncoding() argument
748 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI) in getMemEncoding()
750 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI); in getMemEncoding()
760 SmallVectorImpl<MCFixup> &Fixups, in getMemEncodingMMImm4() argument
765 Fixups, STI) << 4; in getMemEncodingMMImm4()
767 Fixups, STI); in getMemEncodingMMImm4()
774 SmallVectorImpl<MCFixup> &Fixups, in getMemEncodingMMImm4Lsl1() argument
779 Fixups, STI) << 4; in getMemEncodingMMImm4Lsl1()
781 Fixups, STI) >> 1; in getMemEncodingMMImm4Lsl1()
788 SmallVectorImpl<MCFixup> &Fixups, in getMemEncodingMMImm4Lsl2() argument
793 Fixups, STI) << 4; in getMemEncodingMMImm4Lsl2()
795 Fixups, STI) >> 2; in getMemEncodingMMImm4Lsl2()
802 SmallVectorImpl<MCFixup> &Fixups, in getMemEncodingMMSPImm5Lsl2() argument
810 Fixups, STI) >> 2; in getMemEncodingMMSPImm5Lsl2()
817 SmallVectorImpl<MCFixup> &Fixups, in getMemEncodingMMGPImm7Lsl2() argument
825 Fixups, STI) >> 2; in getMemEncodingMMGPImm7Lsl2()
832 SmallVectorImpl<MCFixup> &Fixups, in getMemEncodingMMImm9() argument
836 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, in getMemEncodingMMImm9()
839 getMachineOpValue(MI, MI.getOperand(OpNo + 1), Fixups, STI); in getMemEncodingMMImm9()
846 SmallVectorImpl<MCFixup> &Fixups, in getMemEncodingMMImm11() argument
850 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, in getMemEncodingMMImm11()
852 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI); in getMemEncodingMMImm11()
859 SmallVectorImpl<MCFixup> &Fixups, in getMemEncodingMMImm12() argument
874 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI) in getMemEncodingMMImm12()
876 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI); in getMemEncodingMMImm12()
883 SmallVectorImpl<MCFixup> &Fixups, in getMemEncodingMMImm16() argument
887 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, in getMemEncodingMMImm16()
889 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI); in getMemEncodingMMImm16()
896 SmallVectorImpl<MCFixup> &Fixups, in getMemEncodingMMImm4sp() argument
915 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI); in getMemEncodingMMImm4sp()
924 SmallVectorImpl<MCFixup> &Fixups, in getSizeInsEncoding() argument
928 unsigned Position = getMachineOpValue(MI, MI.getOperand(OpNo-1), Fixups, STI); in getSizeInsEncoding()
929 unsigned Size = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI); in getSizeInsEncoding()
937 SmallVectorImpl<MCFixup> &Fixups, in getUImmWithOffsetEncoding() argument
940 unsigned Value = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI); in getUImmWithOffsetEncoding()
947 SmallVectorImpl<MCFixup> &Fixups, in getSimm19Lsl2Encoding() argument
952 unsigned Res = getMachineOpValue(MI, MO, Fixups, STI); in getSimm19Lsl2Encoding()
961 Mips::Fixups FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_PC19_S2 in getSimm19Lsl2Encoding()
963 Fixups.push_back(MCFixup::create(0, Expr, MCFixupKind(FixupKind))); in getSimm19Lsl2Encoding()
969 SmallVectorImpl<MCFixup> &Fixups, in getSimm18Lsl3Encoding() argument
974 unsigned Res = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI); in getSimm18Lsl3Encoding()
983 Mips::Fixups FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_PC18_S3 in getSimm18Lsl3Encoding()
985 Fixups.push_back(MCFixup::create(0, Expr, MCFixupKind(FixupKind))); in getSimm18Lsl3Encoding()
991 SmallVectorImpl<MCFixup> &Fixups, in getUImm3Mod8Encoding() argument
1000 SmallVectorImpl<MCFixup> &Fixups, in getUImm4AndValue() argument
1028 SmallVectorImpl<MCFixup> &Fixups, in getRegisterListOpValue() argument
1048 SmallVectorImpl<MCFixup> &Fixups, in getRegisterListOpValue16() argument
1055 SmallVectorImpl<MCFixup> &Fixups, in getMovePRegPairOpValue() argument
1089 SmallVectorImpl<MCFixup> &Fixups, in getMovePRegSingleOpValue() argument
1112 SmallVectorImpl<MCFixup> &Fixups, in getSimm23Lsl2Encoding() argument