3470     TOut.emitRR(Mips::MTC1, FirstReg, TmpReg, IDLoc, STI);  in expandLoadSingleImmToFPR()
3590       TOut.emitRR(Mips::DMTC1, FirstReg, TmpReg, IDLoc, STI);  in expandLoadDoubleImmToFPR()
3600       TOut.emitRR(Mips::MTC1, FirstReg, Mips::ZERO, IDLoc, STI);  in expandLoadDoubleImmToFPR()
3603       TOut.emitRR(Mips::MTC1, nextReg(FirstReg), TmpReg, IDLoc, STI);  in expandLoadDoubleImmToFPR()
3604       TOut.emitRR(Mips::MTC1, FirstReg, Mips::ZERO, IDLoc, STI);  in expandLoadDoubleImmToFPR()
4311       TOut.emitRR(DivOp, RsReg, ATReg, IDLoc, STI);  in expandDivRem()
4334     TOut.emitRR(DivOp, RsReg, RtReg, IDLoc, STI);  in expandDivRem()
4352   TOut.emitRR(DivOp, RsReg, RtReg, IDLoc, STI);  in expandDivRem()
4420     TOut.emitRR(Mips::CFC1, ThirdReg, Mips::RA, IDLoc, STI);  in expandTrunc()
4421     TOut.emitRR(Mips::CFC1, ThirdReg, Mips::RA, IDLoc, STI);  in expandTrunc()
4425     TOut.emitRR(Mips::CTC1, Mips::RA, ATReg, IDLoc, STI);  in expandTrunc()
4427     TOut.emitRR(IsDouble ? (Is64FPU ? Mips::CVT_W_D64 : Mips::CVT_W_D32)  in expandTrunc()
4430     TOut.emitRR(Mips::CTC1, Mips::RA, ThirdReg, IDLoc, STI);  in expandTrunc()
4435   TOut.emitRR(IsDouble ? (Is64FPU ? Mips::TRUNC_W_D64 : Mips::TRUNC_W_D32)  in expandTrunc()
5239   TOut.emitRR(Inst.getOpcode() == Mips::MULImmMacro ? Mips::MULT : Mips::DMULT,  in expandMulImm()
5259   TOut.emitRR(Inst.getOpcode() == Mips::MULOMacro ? Mips::MULT : Mips::DMULT,  in expandMulO()
5301   TOut.emitRR(Inst.getOpcode() == Mips::MULOUMacro ? Mips::MULTu : Mips::DMULTu,  in expandMulOU()
5332   TOut.emitRR(Mips::DMULTu, SrcReg, TmpReg, IDLoc, STI);  in expandDMULMacro()
5813       TOut.emitRR(Opcode, RtReg, BaseReg, IDLoc, STI);  in expandSaaAddr()
5825   TOut.emitRR(Opcode, RtReg, ATReg, IDLoc, STI);  in expandSaaAddr()