2930   const MCOperand &DstRegOp = Inst.getOperand(0);  in expandLoadImm()  local
2931   assert(DstRegOp.isReg() && "expected register operand kind");  in expandLoadImm()
2933   if (loadImmediate(ImmOp.getImm(), DstRegOp.getReg(), Mips::NoRegister,  in expandLoadImm()
3684   const MCOperand &DstRegOp = Inst.getOperand(0);  in expandBranchImm()  local
3685   assert(DstRegOp.isReg() && "expected register operand kind");  in expandBranchImm()
3720       TOut.emitRRX(OpCode, DstRegOp.getReg(), Mips::ZERO,  in expandBranchImm()
3724       TOut.emitRRX(OpCode, DstRegOp.getReg(), Mips::ZERO, MemOffsetOp, IDLoc,  in expandBranchImm()
3738       TOut.emitRRX(OpCode, DstRegOp.getReg(), ATReg,  in expandBranchImm()
3742       TOut.emitRRX(OpCode, DstRegOp.getReg(), ATReg, MemOffsetOp, IDLoc, STI);  in expandBranchImm()
3753   const MCOperand &DstRegOp = Inst.getOperand(StartOp);  in expandMem16Inst()  local
3754   assert(DstRegOp.isReg() && "expected register operand kind");  in expandMem16Inst()
3761   unsigned DstReg = DstRegOp.getReg();  in expandMem16Inst()
3880   const MCOperand &DstRegOp = Inst.getOperand(StartOp);  in expandMem9Inst()  local
3881   assert(DstRegOp.isReg() && "expected register operand kind");  in expandMem9Inst()
3888   unsigned DstReg = DstRegOp.getReg();  in expandMem9Inst()
4448   const MCOperand &DstRegOp = Inst.getOperand(0);  in expandUlh()  local
4449   assert(DstRegOp.isReg() && "expected register operand kind");  in expandUlh()
4456   unsigned DstReg = DstRegOp.getReg();  in expandUlh()
4500   const MCOperand &DstRegOp = Inst.getOperand(0);  in expandUsh()  local
4501   assert(DstRegOp.isReg() && "expected register operand kind");  in expandUsh()
4508   unsigned DstReg = DstRegOp.getReg();  in expandUsh()
4551   const MCOperand &DstRegOp = Inst.getOperand(0);  in expandUxw()  local
4552   assert(DstRegOp.isReg() && "expected register operand kind");  in expandUxw()
4559   unsigned DstReg = DstRegOp.getReg();  in expandUxw()