Lines Matching refs:AVR
40 addRegisterClass(MVT::i8, &AVR::GPR8RegClass); in AVRTargetLowering()
41 addRegisterClass(MVT::i16, &AVR::DREGSRegClass); in AVRTargetLowering()
49 setStackPointerRegisterToSaveRestore(AVR::SP); in AVRTargetLowering()
1069 if (isa<PointerType>(Ty) && AS == AVR::ProgramMemory) { in isLegalAddressingMode()
1100 if (AVR::isProgramMemoryAccess(LD)) { in getPreIndexedAddressParts()
1106 if (AVR::isProgramMemoryAccess(ST)) { in getPreIndexedAddressParts()
1158 if (AVR::isProgramMemoryAccess(ST)) in getPostIndexedAddressParts()
1189 if (AVR::isProgramMemoryAccess(LD)) in getPostIndexedAddressParts()
1216 AVR::R25, AVR::R24, AVR::R23, AVR::R22, AVR::R21, AVR::R20,
1217 AVR::R19, AVR::R18, AVR::R17, AVR::R16, AVR::R15, AVR::R14,
1218 AVR::R13, AVR::R12, AVR::R11, AVR::R10, AVR::R9, AVR::R8};
1219 static const MCPhysReg RegList8Tiny[] = {AVR::R25, AVR::R24, AVR::R23,
1220 AVR::R22, AVR::R21, AVR::R20};
1222 AVR::R26R25, AVR::R25R24, AVR::R24R23, AVR::R23R22, AVR::R22R21,
1223 AVR::R21R20, AVR::R20R19, AVR::R19R18, AVR::R18R17, AVR::R17R16,
1224 AVR::R16R15, AVR::R15R14, AVR::R14R13, AVR::R13R12, AVR::R12R11,
1225 AVR::R11R10, AVR::R10R9, AVR::R9R8};
1226 static const MCPhysReg RegList16Tiny[] = {AVR::R26R25, AVR::R25R24,
1227 AVR::R24R23, AVR::R23R22,
1228 AVR::R22R21, AVR::R21R20};
1412 RC = &AVR::GPR8RegClass; in LowerFormalArguments()
1414 RC = &AVR::DREGSRegClass; in LowerFormalArguments()
1594 DAG.getRegister(AVR::SP, getPointerTy(DAG.getDataLayout())), in LowerCall()
1789 case AVR::Lsl8: in insertShift()
1790 Opc = AVR::ADDRdRr; // LSL is an alias of ADD Rd, Rd in insertShift()
1791 RC = &AVR::GPR8RegClass; in insertShift()
1794 case AVR::Lsl16: in insertShift()
1795 Opc = AVR::LSLWRd; in insertShift()
1796 RC = &AVR::DREGSRegClass; in insertShift()
1798 case AVR::Asr8: in insertShift()
1799 Opc = AVR::ASRRd; in insertShift()
1800 RC = &AVR::GPR8RegClass; in insertShift()
1802 case AVR::Asr16: in insertShift()
1803 Opc = AVR::ASRWRd; in insertShift()
1804 RC = &AVR::DREGSRegClass; in insertShift()
1806 case AVR::Lsr8: in insertShift()
1807 Opc = AVR::LSRRd; in insertShift()
1808 RC = &AVR::GPR8RegClass; in insertShift()
1810 case AVR::Lsr16: in insertShift()
1811 Opc = AVR::LSRWRd; in insertShift()
1812 RC = &AVR::DREGSRegClass; in insertShift()
1814 case AVR::Rol8: in insertShift()
1815 Opc = Tiny ? AVR::ROLBRdR17 : AVR::ROLBRdR1; in insertShift()
1816 RC = &AVR::GPR8RegClass; in insertShift()
1818 case AVR::Rol16: in insertShift()
1819 Opc = AVR::ROLWRd; in insertShift()
1820 RC = &AVR::DREGSRegClass; in insertShift()
1822 case AVR::Ror8: in insertShift()
1823 Opc = AVR::RORBRd; in insertShift()
1824 RC = &AVR::GPR8RegClass; in insertShift()
1826 case AVR::Ror16: in insertShift()
1827 Opc = AVR::RORWRd; in insertShift()
1828 RC = &AVR::DREGSRegClass; in insertShift()
1861 Register ShiftAmtReg = RI.createVirtualRegister(&AVR::GPR8RegClass); in insertShift()
1862 Register ShiftAmtReg2 = RI.createVirtualRegister(&AVR::GPR8RegClass); in insertShift()
1871 BuildMI(BB, dl, TII.get(AVR::RJMPk)).addMBB(CheckBB); in insertShift()
1885 BuildMI(CheckBB, dl, TII.get(AVR::PHI), ShiftReg) in insertShift()
1890 BuildMI(CheckBB, dl, TII.get(AVR::PHI), ShiftAmtReg) in insertShift()
1895 BuildMI(CheckBB, dl, TII.get(AVR::PHI), DstReg) in insertShift()
1901 BuildMI(CheckBB, dl, TII.get(AVR::DECRd), ShiftAmtReg2).addReg(ShiftAmtReg); in insertShift()
1902 BuildMI(CheckBB, dl, TII.get(AVR::BRPLk)).addMBB(LoopBB); in insertShift()
1931 Register ZeroReg = MRI.createVirtualRegister(&AVR::GPR8RegClass); in insertMultibyteShift()
1932 BuildMI(*BB, MI, dl, TII.get(AVR::COPY), ZeroReg) in insertMultibyteShift()
1955 Register LowByte = MRI.createVirtualRegister(&AVR::GPR8RegClass); in insertMultibyteShift()
1956 BuildMI(*BB, MI, dl, TII.get(AVR::RORRd), LowByte).addReg(ZeroReg); in insertMultibyteShift()
1961 Register NewLowByte = MRI.createVirtualRegister(&AVR::GPR8RegClass); in insertMultibyteShift()
1962 BuildMI(*BB, MI, dl, TII.get(AVR::RORRd), NewLowByte).addReg(LowByte); in insertMultibyteShift()
1996 Register HighByte = MRI.createVirtualRegister(&AVR::GPR8RegClass); in insertMultibyteShift()
2000 BuildMI(*BB, MI, dl, TII.get(AVR::SBCRdRr), HighByte) in insertMultibyteShift()
2010 BuildMI(*BB, MI, dl, TII.get(AVR::ADCRdRr), HighByte) in insertMultibyteShift()
2019 Register NewExt = MRI.createVirtualRegister(&AVR::GPR8RegClass); in insertMultibyteShift()
2020 BuildMI(*BB, MI, dl, TII.get(AVR::ADCRdRr), NewExt) in insertMultibyteShift()
2063 ShrExtendReg = MRI.createVirtualRegister(&AVR::GPR8RegClass); in insertMultibyteShift()
2064 Register Tmp = MRI.createVirtualRegister(&AVR::GPR8RegClass); in insertMultibyteShift()
2065 BuildMI(*BB, MI, dl, TII.get(AVR::ADDRdRr), Tmp) in insertMultibyteShift()
2068 BuildMI(*BB, MI, dl, TII.get(AVR::SBCRdRr), ShrExtendReg) in insertMultibyteShift()
2113 Register SwapReg = MRI.createVirtualRegister(&AVR::LD8RegClass); in insertMultibyteShift()
2114 BuildMI(*BB, MI, dl, TII.get(AVR::SWAPRd), SwapReg) in insertMultibyteShift()
2117 Register R = MRI.createVirtualRegister(&AVR::GPR8RegClass); in insertMultibyteShift()
2118 BuildMI(*BB, MI, dl, TII.get(AVR::EORRdRr), R) in insertMultibyteShift()
2123 Register AndReg = MRI.createVirtualRegister(&AVR::LD8RegClass); in insertMultibyteShift()
2124 BuildMI(*BB, MI, dl, TII.get(AVR::ANDIRdK), AndReg) in insertMultibyteShift()
2128 Register R = MRI.createVirtualRegister(&AVR::GPR8RegClass); in insertMultibyteShift()
2129 BuildMI(*BB, MI, dl, TII.get(AVR::EORRdRr), R) in insertMultibyteShift()
2146 Register Out = MRI.createVirtualRegister(&AVR::GPR8RegClass); in insertMultibyteShift()
2150 BuildMI(*BB, MI, dl, TII.get(AVR::ADDRdRr), Out) in insertMultibyteShift()
2154 BuildMI(*BB, MI, dl, TII.get(AVR::ADCRdRr), Out) in insertMultibyteShift()
2165 Register Out = MRI.createVirtualRegister(&AVR::GPR8RegClass); in insertMultibyteShift()
2169 unsigned Opc = ArithmeticShift ? AVR::ASRRd : AVR::LSRRd; in insertMultibyteShift()
2172 BuildMI(*BB, MI, dl, TII.get(AVR::RORRd), Out).addReg(In, 0, InSubreg); in insertMultibyteShift()
2196 case AVR::Lsl32: in insertWideShift()
2199 case AVR::Lsr32: in insertWideShift()
2202 case AVR::Asr32: in insertWideShift()
2209 std::pair(MI.getOperand(3).getReg(), AVR::sub_hi), in insertWideShift()
2210 std::pair(MI.getOperand(3).getReg(), AVR::sub_lo), in insertWideShift()
2211 std::pair(MI.getOperand(2).getReg(), AVR::sub_hi), in insertWideShift()
2212 std::pair(MI.getOperand(2).getReg(), AVR::sub_lo), in insertWideShift()
2232 BuildMI(*BB, MI, dl, TII.get(AVR::REG_SEQUENCE), MI.getOperand(0).getReg()) in insertWideShift()
2234 .addImm(AVR::sub_lo) in insertWideShift()
2236 .addImm(AVR::sub_hi); in insertWideShift()
2237 BuildMI(*BB, MI, dl, TII.get(AVR::REG_SEQUENCE), MI.getOperand(1).getReg()) in insertWideShift()
2239 .addImm(AVR::sub_lo) in insertWideShift()
2241 .addImm(AVR::sub_hi); in insertWideShift()
2244 BuildMI(*BB, MI, dl, TII.get(AVR::REG_SEQUENCE), MI.getOperand(1).getReg()) in insertWideShift()
2246 .addImm(AVR::sub_hi) in insertWideShift()
2248 .addImm(AVR::sub_lo); in insertWideShift()
2249 BuildMI(*BB, MI, dl, TII.get(AVR::REG_SEQUENCE), MI.getOperand(0).getReg()) in insertWideShift()
2251 .addImm(AVR::sub_hi) in insertWideShift()
2253 .addImm(AVR::sub_lo); in insertWideShift()
2262 if (I->getOpcode() == AVR::COPY) { in isCopyMulResult()
2264 return (SrcReg == AVR::R0 || SrcReg == AVR::R1); in isCopyMulResult()
2282 BuildMI(*BB, I, MI.getDebugLoc(), TII.get(AVR::EORRdRr), AVR::R1) in insertMul()
2283 .addReg(AVR::R1) in insertMul()
2284 .addReg(AVR::R1); in insertMul()
2294 BuildMI(*BB, I, MI.getDebugLoc(), TII.get(AVR::COPY)) in insertCopyZero()
2320 (Width == 8) ? &AVR::GPR8RegClass : &AVR::DREGSRegClass; in insertAtomicArithmeticOp()
2321 unsigned LoadOpcode = (Width == 8) ? AVR::LDRdPtr : AVR::LDWRdPtr; in insertAtomicArithmeticOp()
2322 unsigned StoreOpcode = (Width == 8) ? AVR::STPtrRr : AVR::STWPtrRr; in insertAtomicArithmeticOp()
2325 BuildMI(*BB, I, dl, TII.get(AVR::INRdA), Subtarget.getTmpRegister()) in insertAtomicArithmeticOp()
2327 BuildMI(*BB, I, dl, TII.get(AVR::BCLRs)).addImm(7); in insertAtomicArithmeticOp()
2345 BuildMI(*BB, I, dl, TII.get(AVR::OUTARr)) in insertAtomicArithmeticOp()
2363 case AVR::Lsl8: in EmitInstrWithCustomInserter()
2364 case AVR::Lsl16: in EmitInstrWithCustomInserter()
2365 case AVR::Lsr8: in EmitInstrWithCustomInserter()
2366 case AVR::Lsr16: in EmitInstrWithCustomInserter()
2367 case AVR::Rol8: in EmitInstrWithCustomInserter()
2368 case AVR::Rol16: in EmitInstrWithCustomInserter()
2369 case AVR::Ror8: in EmitInstrWithCustomInserter()
2370 case AVR::Ror16: in EmitInstrWithCustomInserter()
2371 case AVR::Asr8: in EmitInstrWithCustomInserter()
2372 case AVR::Asr16: in EmitInstrWithCustomInserter()
2374 case AVR::Lsl32: in EmitInstrWithCustomInserter()
2375 case AVR::Lsr32: in EmitInstrWithCustomInserter()
2376 case AVR::Asr32: in EmitInstrWithCustomInserter()
2378 case AVR::MULRdRr: in EmitInstrWithCustomInserter()
2379 case AVR::MULSRdRr: in EmitInstrWithCustomInserter()
2381 case AVR::CopyZero: in EmitInstrWithCustomInserter()
2383 case AVR::AtomicLoadAdd8: in EmitInstrWithCustomInserter()
2384 return insertAtomicArithmeticOp(MI, MBB, AVR::ADDRdRr, 8); in EmitInstrWithCustomInserter()
2385 case AVR::AtomicLoadAdd16: in EmitInstrWithCustomInserter()
2386 return insertAtomicArithmeticOp(MI, MBB, AVR::ADDWRdRr, 16); in EmitInstrWithCustomInserter()
2387 case AVR::AtomicLoadSub8: in EmitInstrWithCustomInserter()
2388 return insertAtomicArithmeticOp(MI, MBB, AVR::SUBRdRr, 8); in EmitInstrWithCustomInserter()
2389 case AVR::AtomicLoadSub16: in EmitInstrWithCustomInserter()
2390 return insertAtomicArithmeticOp(MI, MBB, AVR::SUBWRdRr, 16); in EmitInstrWithCustomInserter()
2391 case AVR::AtomicLoadAnd8: in EmitInstrWithCustomInserter()
2392 return insertAtomicArithmeticOp(MI, MBB, AVR::ANDRdRr, 8); in EmitInstrWithCustomInserter()
2393 case AVR::AtomicLoadAnd16: in EmitInstrWithCustomInserter()
2394 return insertAtomicArithmeticOp(MI, MBB, AVR::ANDWRdRr, 16); in EmitInstrWithCustomInserter()
2395 case AVR::AtomicLoadOr8: in EmitInstrWithCustomInserter()
2396 return insertAtomicArithmeticOp(MI, MBB, AVR::ORRdRr, 8); in EmitInstrWithCustomInserter()
2397 case AVR::AtomicLoadOr16: in EmitInstrWithCustomInserter()
2398 return insertAtomicArithmeticOp(MI, MBB, AVR::ORWRdRr, 16); in EmitInstrWithCustomInserter()
2399 case AVR::AtomicLoadXor8: in EmitInstrWithCustomInserter()
2400 return insertAtomicArithmeticOp(MI, MBB, AVR::EORRdRr, 8); in EmitInstrWithCustomInserter()
2401 case AVR::AtomicLoadXor16: in EmitInstrWithCustomInserter()
2402 return insertAtomicArithmeticOp(MI, MBB, AVR::EORWRdRr, 16); in EmitInstrWithCustomInserter()
2405 assert((Opc == AVR::Select16 || Opc == AVR::Select8) && in EmitInstrWithCustomInserter()
2428 BuildMI(MBB, dl, TII.get(AVR::RJMPk)).addMBB(FallThrough); in EmitInstrWithCustomInserter()
2456 BuildMI(MBB, dl, TII.get(AVR::RJMPk)).addMBB(falseMBB); in EmitInstrWithCustomInserter()
2461 BuildMI(falseMBB, dl, TII.get(AVR::RJMPk)).addMBB(trueMBB); in EmitInstrWithCustomInserter()
2465 BuildMI(*trueMBB, trueMBB->begin(), dl, TII.get(AVR::PHI), in EmitInstrWithCustomInserter()
2658 return std::make_pair(0U, &AVR::LD8loRegClass); in getRegForInlineAsmConstraint()
2660 return std::make_pair(0U, &AVR::DREGSLD8loRegClass); in getRegForInlineAsmConstraint()
2664 return std::make_pair(0U, &AVR::PTRDISPREGSRegClass); in getRegForInlineAsmConstraint()
2668 return std::make_pair(0U, &AVR::LD8RegClass); in getRegForInlineAsmConstraint()
2670 return std::make_pair(0U, &AVR::DLDREGSRegClass); in getRegForInlineAsmConstraint()
2674 return std::make_pair(0U, &AVR::GPR8loRegClass); in getRegForInlineAsmConstraint()
2676 return std::make_pair(0U, &AVR::DREGSloRegClass); in getRegForInlineAsmConstraint()
2680 return std::make_pair(0U, &AVR::PTRREGSRegClass); in getRegForInlineAsmConstraint()
2683 return std::make_pair(0U, &AVR::GPRSPRegClass); in getRegForInlineAsmConstraint()
2686 return std::make_pair(0U, &AVR::GPR8RegClass); in getRegForInlineAsmConstraint()
2688 return std::make_pair(0U, &AVR::DREGSRegClass); in getRegForInlineAsmConstraint()
2693 &AVR::GPR8RegClass); in getRegForInlineAsmConstraint()
2697 return std::make_pair(0U, &AVR::IWREGSRegClass); in getRegForInlineAsmConstraint()
2702 return std::make_pair(unsigned(AVR::R27R26), &AVR::PTRREGSRegClass); in getRegForInlineAsmConstraint()
2707 return std::make_pair(unsigned(AVR::R29R28), &AVR::PTRREGSRegClass); in getRegForInlineAsmConstraint()
2712 return std::make_pair(unsigned(AVR::R31R30), &AVR::PTRREGSRegClass); in getRegForInlineAsmConstraint()
2836 .Case("r0", AVR::R0) in getRegisterByName()
2837 .Case("r1", AVR::R1) in getRegisterByName()
2841 .Case("r0", AVR::R1R0) in getRegisterByName()
2842 .Case("sp", AVR::SP) in getRegisterByName()