63                                     const DebugLoc &dl, unsigned DestReg,  in emitThumb1LoadConstPool()  argument
76     .addReg(DestReg, getDefRegState(true), SubIdx)  in emitThumb1LoadConstPool()
83                                     const DebugLoc &dl, unsigned DestReg,  in emitThumb2LoadConstPool()  argument
95       .addReg(DestReg, getDefRegState(true), SubIdx)  in emitThumb2LoadConstPool()
105     const DebugLoc &dl, Register DestReg, unsigned SubIdx, int Val,  in emitLoadConstPool()  argument
110     assert((isARMLowRegister(DestReg) || DestReg.isVirtual()) &&  in emitLoadConstPool()
112     return emitThumb1LoadConstPool(MBB, MBBI, dl, DestReg, SubIdx, Val, Pred,  in emitLoadConstPool()
115   return emitThumb2LoadConstPool(MBB, MBBI, dl, DestReg, SubIdx, Val, Pred,  in emitLoadConstPool()
126     const DebugLoc &dl, Register DestReg, Register BaseReg, int NumBytes,  in emitThumbRegPlusImmInReg()  argument
134       (DestReg.isVirtual() || isARMLowRegister(DestReg)) && NumBytes >= 0 &&  in emitThumbRegPlusImmInReg()
136     BuildMI(MBB, MBBI, dl, TII.get(ARM::tADDrSPi), DestReg)  in emitThumbRegPlusImmInReg()
144   bool isHigh = !isARMLowRegister(DestReg) ||  in emitThumbRegPlusImmInReg()
155   Register LdReg = DestReg;  in emitThumbRegPlusImmInReg()
156   if (DestReg == ARM::SP)  in emitThumbRegPlusImmInReg()
158   if (!isARMLowRegister(DestReg) && !DestReg.isVirtual())  in emitThumbRegPlusImmInReg()
237   MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg);  in emitThumbRegPlusImmInReg()
240   if (DestReg == ARM::SP || isSub)  in emitThumbRegPlusImmInReg()
253                                      const DebugLoc &dl, Register DestReg,  in emitThumbRegPlusImmediate()  argument
284   if (DestReg == ARM::SP) {  in emitThumbRegPlusImmediate()
296   } else if (isARMLowRegister(DestReg)) {  in emitThumbRegPlusImmediate()
303     } else if (DestReg == BaseReg) {  in emitThumbRegPlusImmediate()
320     if (DestReg == BaseReg) {  in emitThumbRegPlusImmediate()
362   unsigned Threshold = (DestReg == ARM::SP) ? 3 : 2;  in emitThumbRegPlusImmediate()
367                              DestReg, BaseReg, NumBytes, true,  in emitThumbRegPlusImmediate()
377     MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(CopyOpc), DestReg);  in emitThumbRegPlusImmediate()
386     BaseReg = DestReg;  in emitThumbRegPlusImmediate()
394     MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(ExtraOpc), DestReg);  in emitThumbRegPlusImmediate()
441     Register DestReg = MI.getOperand(0).getReg();  in rewriteFrameIndex()  local
443     emitThumbRegPlusImmediate(MBB, II, dl, DestReg, FrameReg, Offset, TII,  in rewriteFrameIndex()
466       Register DestReg = FrameReg;  in rewriteFrameIndex()  local
471         DestReg = MF.getRegInfo().createVirtualRegister(&ARM::tGPRRegClass);  in rewriteFrameIndex()
472         BuildMI(MBB, II, dl, TII.get(ARM::tMOVr), DestReg)  in rewriteFrameIndex()
477       MI.getOperand(FrameRegIdx).ChangeToRegister(DestReg, false);  in rewriteFrameIndex()