Lines Matching refs:Operands
448 bool validatetLDMRegList(const MCInst &Inst, const OperandVector &Operands,
450 bool validatetSTMRegList(const MCInst &Inst, const OperandVector &Operands,
519 OperandVector &Operands);
520 bool CDEConvertDualRegOperand(StringRef Mnemonic, OperandVector &Operands);
662 bool shouldOmitCCOutOperand(StringRef Mnemonic, OperandVector &Operands);
663 bool shouldOmitPredicateOperand(StringRef Mnemonic, OperandVector &Operands);
664 bool shouldOmitVectorPredicateOperand(StringRef Mnemonic, OperandVector &Operands);
666 void fixupGNULDRDAlias(StringRef Mnemonic, OperandVector &Operands);
667 bool validateLDRDSTRD(MCInst &Inst, const OperandVector &Operands,
711 SMLoc NameLoc, OperandVector &Operands) override;
719 OperandVector &Operands, MCStreamer &Out,
722 unsigned MatchInstruction(OperandVector &Operands, MCInst &Inst,
736 SMLoc IDLoc, OperandVector &Operands);
738 OperandVector &Operands);
4129 int ARMAsmParser::tryParseShiftRegister(OperandVector &Operands) { in tryParseShiftRegister() argument
4155 (ARMOperand *)Operands.pop_back_val().release()); in tryParseShiftRegister()
4215 Operands.push_back(ARMOperand::CreateShiftedRegister(ShiftTy, SrcReg, in tryParseShiftRegister()
4219 Operands.push_back(ARMOperand::CreateShiftedImmediate(ShiftTy, SrcReg, Imm, in tryParseShiftRegister()
4231 bool ARMAsmParser::tryParseRegisterWithWriteBack(OperandVector &Operands) { in tryParseRegisterWithWriteBack() argument
4239 Operands.push_back(ARMOperand::CreateReg(RegNo, RegStartLoc, RegEndLoc)); in tryParseRegisterWithWriteBack()
4243 Operands.push_back(ARMOperand::CreateToken(ExclaimTok.getString(), in tryParseRegisterWithWriteBack()
4269 Operands.push_back(ARMOperand::CreateVectorIndex(MCE->getValue(), in tryParseRegisterWithWriteBack()
4327 ParseStatus ARMAsmParser::parseITCondCode(OperandVector &Operands) { in parseITCondCode() argument
4338 Operands.push_back(ARMOperand::CreateCondCode(ARMCC::CondCodes(CC), S)); in parseITCondCode()
4346 ParseStatus ARMAsmParser::parseCoprocNumOperand(OperandVector &Operands) { in parseCoprocNumOperand() argument
4360 Operands.push_back(ARMOperand::CreateCoprocNum(Num, S)); in parseCoprocNumOperand()
4367 ParseStatus ARMAsmParser::parseCoprocRegOperand(OperandVector &Operands) { in parseCoprocRegOperand() argument
4379 Operands.push_back(ARMOperand::CreateCoprocReg(Reg, S)); in parseCoprocRegOperand()
4385 ParseStatus ARMAsmParser::parseCoprocOptionOperand(OperandVector &Operands) { in parseCoprocOptionOperand() argument
4410 Operands.push_back(ARMOperand::CreateCoprocOption(Val, S, E)); in parseCoprocOptionOperand()
4455 bool ARMAsmParser::parseRegisterList(OperandVector &Operands, bool EnforceOrder, in parseRegisterList() argument
4613 Operands.push_back(ARMOperand::CreateRegList(Registers, S, E)); in parseRegisterList()
4617 Operands.push_back(ARMOperand::CreateToken("^",Parser.getTok().getLoc())); in parseRegisterList()
4669 ParseStatus ARMAsmParser::parseVectorList(OperandVector &Operands) { in parseVectorList() argument
4688 Operands.push_back(ARMOperand::CreateVectorList(Reg, 1, false, S, E)); in parseVectorList()
4691 Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 1, false, in parseVectorList()
4695 Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 1, in parseVectorList()
4711 Operands.push_back(ARMOperand::CreateVectorList(Reg, 2, false, S, E)); in parseVectorList()
4716 Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 2, false, in parseVectorList()
4720 Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 2, in parseVectorList()
4880 Operands.push_back(Create(FirstReg, Count, (Spacing == 2), S, E)); in parseVectorList()
4884 Operands.push_back(ARMOperand::CreateVectorListIndexed(FirstReg, Count, in parseVectorList()
4894 ParseStatus ARMAsmParser::parseMemBarrierOptOperand(OperandVector &Operands) { in parseMemBarrierOptOperand() argument
4954 Operands.push_back(ARMOperand::CreateMemBarrierOpt((ARM_MB::MemBOpt)Opt, S)); in parseMemBarrierOptOperand()
4959 ARMAsmParser::parseTraceSyncBarrierOptOperand(OperandVector &Operands) { in parseTraceSyncBarrierOptOperand() argument
4972 Operands.push_back(ARMOperand::CreateTraceSyncBarrierOpt(ARM_TSB::CSYNC, S)); in parseTraceSyncBarrierOptOperand()
4978 ARMAsmParser::parseInstSyncBarrierOptOperand(OperandVector &Operands) { in parseInstSyncBarrierOptOperand() argument
5016 Operands.push_back(ARMOperand::CreateInstSyncBarrierOpt( in parseInstSyncBarrierOptOperand()
5022 ParseStatus ARMAsmParser::parseProcIFlagsOperand(OperandVector &Operands) { in parseProcIFlagsOperand() argument
5051 Operands.push_back(ARMOperand::CreateProcIFlags((ARM_PROC::IFlags)IFlags, S)); in parseProcIFlagsOperand()
5056 ParseStatus ARMAsmParser::parseMSRMaskOperand(OperandVector &Operands) { in parseMSRMaskOperand() argument
5068 Operands.push_back(ARMOperand::CreateMSRMask(SYSmvalue, S)); in parseMSRMaskOperand()
5084 Operands.push_back(ARMOperand::CreateMSRMask(SYSmvalue, S)); in parseMSRMaskOperand()
5147 Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S)); in parseMSRMaskOperand()
5153 ParseStatus ARMAsmParser::parseBankedRegOperand(OperandVector &Operands) { in parseBankedRegOperand() argument
5167 Operands.push_back(ARMOperand::CreateBankedReg(Encoding, S)); in parseBankedRegOperand()
5171 ParseStatus ARMAsmParser::parsePKHImm(OperandVector &Operands, StringRef Op, in parsePKHImm() argument
5202 Operands.push_back(ARMOperand::CreateImm(CE, Loc, EndLoc)); in parsePKHImm()
5207 ParseStatus ARMAsmParser::parseSetEndImm(OperandVector &Operands) { in parseSetEndImm() argument
5221 Operands.push_back(ARMOperand::CreateImm(MCConstantExpr::create(Val, in parseSetEndImm()
5232 ParseStatus ARMAsmParser::parseShifterImm(OperandVector &Operands) { in parseShifterImm() argument
5278 Operands.push_back(ARMOperand::CreateShifterImm(isASR, Val, S, EndLoc)); in parseShifterImm()
5286 ParseStatus ARMAsmParser::parseRotImm(OperandVector &Operands) { in parseRotImm() argument
5319 Operands.push_back(ARMOperand::CreateRotImm(Val, S, EndLoc)); in parseRotImm()
5324 ParseStatus ARMAsmParser::parseModImm(OperandVector &Operands) { in parseModImm() argument
5369 Operands.push_back(ARMOperand::CreateModImm((Enc & 0xFF), in parseModImm()
5382 Operands.push_back(ARMOperand::CreateImm(Imm1Exp, Sx1, Ex1)); in parseModImm()
5388 Operands.push_back(ARMOperand::CreateImm(Imm1Exp, Sx1, Ex1)); in parseModImm()
5422 Operands.push_back(ARMOperand::CreateModImm(Imm1, Imm2, S, Ex2)); in parseModImm()
5432 ParseStatus ARMAsmParser::parseBitfield(OperandVector &Operands) { in parseBitfield() argument
5477 Operands.push_back(ARMOperand::CreateBitfield(LSB, Width, S, EndLoc)); in parseBitfield()
5482 ParseStatus ARMAsmParser::parsePostIdxReg(OperandVector &Operands) { in parsePostIdxReg() argument
5524 Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ShiftTy, in parsePostIdxReg()
5530 ParseStatus ARMAsmParser::parseAM3Offset(OperandVector &Operands) { in parseAM3Offset() argument
5566 Operands.push_back( in parseAM3Offset()
5591 Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ARM_AM::no_shift, in parseAM3Offset()
5601 const OperandVector &Operands) { in cvtThumbMultiply() argument
5602 ((ARMOperand &)*Operands[3]).addRegOperands(Inst, 1); in cvtThumbMultiply()
5603 ((ARMOperand &)*Operands[1]).addCCOutOperands(Inst, 1); in cvtThumbMultiply()
5607 if (Operands.size() == 6 && in cvtThumbMultiply()
5608 ((ARMOperand &)*Operands[4]).getReg() == in cvtThumbMultiply()
5609 ((ARMOperand &)*Operands[3]).getReg()) in cvtThumbMultiply()
5611 ((ARMOperand &)*Operands[RegOp]).addRegOperands(Inst, 1); in cvtThumbMultiply()
5613 ((ARMOperand &)*Operands[2]).addCondCodeOperands(Inst, 2); in cvtThumbMultiply()
5617 const OperandVector &Operands) { in cvtThumbBranches() argument
5640 unsigned Cond = static_cast<ARMOperand &>(*Operands[CondOp]).getCondCode(); in cvtThumbBranches()
5657 ARMOperand &op = static_cast<ARMOperand &>(*Operands[ImmOp]); in cvtThumbBranches()
5664 ARMOperand &op = static_cast<ARMOperand &>(*Operands[ImmOp]); in cvtThumbBranches()
5670 ((ARMOperand &)*Operands[ImmOp]).addImmOperands(Inst, 1); in cvtThumbBranches()
5671 ((ARMOperand &)*Operands[CondOp]).addCondCodeOperands(Inst, 2); in cvtThumbBranches()
5675 MCInst &Inst, const OperandVector &Operands) { in cvtMVEVMOVQtoDReg() argument
5678 assert(Operands.size() == 8); in cvtMVEVMOVQtoDReg()
5680 ((ARMOperand &)*Operands[2]).addRegOperands(Inst, 1); // Rt in cvtMVEVMOVQtoDReg()
5681 ((ARMOperand &)*Operands[3]).addRegOperands(Inst, 1); // Rt2 in cvtMVEVMOVQtoDReg()
5682 ((ARMOperand &)*Operands[4]).addRegOperands(Inst, 1); // Qd in cvtMVEVMOVQtoDReg()
5683 ((ARMOperand &)*Operands[5]).addMVEPairVectorIndexOperands(Inst, 1); // idx in cvtMVEVMOVQtoDReg()
5685 ((ARMOperand &)*Operands[7]).addMVEPairVectorIndexOperands(Inst, 1); // idx2 in cvtMVEVMOVQtoDReg()
5686 ((ARMOperand &)*Operands[1]).addCondCodeOperands(Inst, 2); // condition code in cvtMVEVMOVQtoDReg()
5691 bool ARMAsmParser::parseMemory(OperandVector &Operands) { in parseMemory() argument
5714 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, nullptr, 0, in parseMemory()
5721 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc())); in parseMemory()
5771 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, nullptr, 0, in parseMemory()
5778 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc())); in parseMemory()
5814 Operands.push_back(ARMOperand::CreateMem( in parseMemory()
5826 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc())); in parseMemory()
5863 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, nullptr, OffsetRegNum, in parseMemory()
5870 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc())); in parseMemory()
5944 ParseStatus ARMAsmParser::parseFPImm(OperandVector &Operands) { in parseFPImm() argument
5971 ARMOperand &TyOp = static_cast<ARMOperand &>(*Operands[2]); in parseFPImm()
5975 ARMOperand &Mnemonic = static_cast<ARMOperand &>(*Operands[0]); in parseFPImm()
5997 Operands.push_back(ARMOperand::CreateImm( in parseFPImm()
6012 Operands.push_back(ARMOperand::CreateImm( in parseFPImm()
6023 bool ARMAsmParser::parseOperand(OperandVector &Operands, StringRef Mnemonic) { in parseOperand() argument
6029 ParseStatus ResTy = MatchOperandParserImpl(Operands, Mnemonic); in parseOperand()
6048 if (!tryParseRegisterWithWriteBack(Operands)) in parseOperand()
6050 int Res = tryParseShiftRegister(Operands); in parseOperand()
6060 Operands.push_back(ARMOperand::CreateToken("APSR_nzcv", S)); in parseOperand()
6080 Operands.push_back(ARMOperand::CreateImm(IdVal, S, E)); in parseOperand()
6084 return parseMemory(Operands); in parseOperand()
6086 return parseRegisterList(Operands, !Mnemonic.starts_with("clr")); in parseOperand()
6121 Operands.push_back(ARMOperand::CreateImm(ImmVal, S, E)); in parseOperand()
6127 Operands.push_back(ARMOperand::CreateToken(Parser.getTok().getString(), in parseOperand()
6153 Operands.push_back(ARMOperand::CreateImm(ExprVal, S, E)); in parseOperand()
6168 Operands.push_back(ARMOperand::CreateConstantPoolImm(SubExprVal, S, E)); in parseOperand()
6493 OperandVector &Operands) { in tryConvertingToTwoOperandForm() argument
6494 if (Operands.size() != 6) in tryConvertingToTwoOperandForm()
6497 const auto &Op3 = static_cast<ARMOperand &>(*Operands[3]); in tryConvertingToTwoOperandForm()
6498 auto &Op4 = static_cast<ARMOperand &>(*Operands[4]); in tryConvertingToTwoOperandForm()
6509 auto &Op5 = static_cast<ARMOperand &>(*Operands[5]); in tryConvertingToTwoOperandForm()
6569 Operands.erase(Operands.begin() + 3); in tryConvertingToTwoOperandForm()
6595 OperandVector &Operands) { in shouldOmitCCOutOperand() argument
6607 if (Mnemonic == "mov" && Operands.size() > 4 && !isThumb() && in shouldOmitCCOutOperand()
6608 !static_cast<ARMOperand &>(*Operands[4]).isModImm() && in shouldOmitCCOutOperand()
6609 static_cast<ARMOperand &>(*Operands[4]).isImm0_65535Expr() && in shouldOmitCCOutOperand()
6610 static_cast<ARMOperand &>(*Operands[1]).getReg() == 0) in shouldOmitCCOutOperand()
6613 if (Mnemonic == "movs" && Operands.size() > 3 && isThumb() && in shouldOmitCCOutOperand()
6614 isThumbI8Relocation(*Operands[3])) in shouldOmitCCOutOperand()
6619 if (isThumb() && Mnemonic == "add" && Operands.size() == 5 && in shouldOmitCCOutOperand()
6620 static_cast<ARMOperand &>(*Operands[3]).isReg() && in shouldOmitCCOutOperand()
6621 static_cast<ARMOperand &>(*Operands[4]).isReg() && in shouldOmitCCOutOperand()
6622 static_cast<ARMOperand &>(*Operands[1]).getReg() == 0) in shouldOmitCCOutOperand()
6630 Operands.size() == 6 && static_cast<ARMOperand &>(*Operands[3]).isReg() && in shouldOmitCCOutOperand()
6631 static_cast<ARMOperand &>(*Operands[4]).isReg() && in shouldOmitCCOutOperand()
6632 static_cast<ARMOperand &>(*Operands[4]).getReg() == ARM::SP && in shouldOmitCCOutOperand()
6633 static_cast<ARMOperand &>(*Operands[1]).getReg() == 0 && in shouldOmitCCOutOperand()
6634 ((Mnemonic == "add" && static_cast<ARMOperand &>(*Operands[5]).isReg()) || in shouldOmitCCOutOperand()
6635 static_cast<ARMOperand &>(*Operands[5]).isImm0_1020s4())) in shouldOmitCCOutOperand()
6643 Operands.size() == 6 && static_cast<ARMOperand &>(*Operands[3]).isReg() && in shouldOmitCCOutOperand()
6644 static_cast<ARMOperand &>(*Operands[4]).isReg() && in shouldOmitCCOutOperand()
6645 static_cast<ARMOperand &>(*Operands[5]).isImm()) { in shouldOmitCCOutOperand()
6651 isARMLowRegister(static_cast<ARMOperand &>(*Operands[3]).getReg()) && in shouldOmitCCOutOperand()
6652 isARMLowRegister(static_cast<ARMOperand &>(*Operands[4]).getReg()) && in shouldOmitCCOutOperand()
6653 static_cast<ARMOperand &>(*Operands[5]).isImm0_7()) in shouldOmitCCOutOperand()
6657 if (static_cast<ARMOperand &>(*Operands[4]).getReg() != ARM::PC && in shouldOmitCCOutOperand()
6658 (static_cast<ARMOperand &>(*Operands[5]).isT2SOImm() || in shouldOmitCCOutOperand()
6659 static_cast<ARMOperand &>(*Operands[5]).isT2SOImmNeg())) in shouldOmitCCOutOperand()
6670 if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 6 && in shouldOmitCCOutOperand()
6671 static_cast<ARMOperand &>(*Operands[1]).getReg() == 0 && in shouldOmitCCOutOperand()
6672 static_cast<ARMOperand &>(*Operands[3]).isReg() && in shouldOmitCCOutOperand()
6673 static_cast<ARMOperand &>(*Operands[4]).isReg() && in shouldOmitCCOutOperand()
6674 static_cast<ARMOperand &>(*Operands[5]).isReg() && in shouldOmitCCOutOperand()
6679 (!isARMLowRegister(static_cast<ARMOperand &>(*Operands[3]).getReg()) || in shouldOmitCCOutOperand()
6680 !isARMLowRegister(static_cast<ARMOperand &>(*Operands[4]).getReg()) || in shouldOmitCCOutOperand()
6681 !isARMLowRegister(static_cast<ARMOperand &>(*Operands[5]).getReg()) || in shouldOmitCCOutOperand()
6682 !inITBlock() || (static_cast<ARMOperand &>(*Operands[3]).getReg() != in shouldOmitCCOutOperand()
6683 static_cast<ARMOperand &>(*Operands[5]).getReg() && in shouldOmitCCOutOperand()
6684 static_cast<ARMOperand &>(*Operands[3]).getReg() != in shouldOmitCCOutOperand()
6685 static_cast<ARMOperand &>(*Operands[4]).getReg()))) in shouldOmitCCOutOperand()
6690 if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 5 && in shouldOmitCCOutOperand()
6691 static_cast<ARMOperand &>(*Operands[1]).getReg() == 0 && in shouldOmitCCOutOperand()
6692 static_cast<ARMOperand &>(*Operands[3]).isReg() && in shouldOmitCCOutOperand()
6693 static_cast<ARMOperand &>(*Operands[4]).isReg() && in shouldOmitCCOutOperand()
6697 (!isARMLowRegister(static_cast<ARMOperand &>(*Operands[3]).getReg()) || in shouldOmitCCOutOperand()
6698 !isARMLowRegister(static_cast<ARMOperand &>(*Operands[4]).getReg()) || in shouldOmitCCOutOperand()
6708 (Operands.size() == 5 || Operands.size() == 6) && in shouldOmitCCOutOperand()
6709 static_cast<ARMOperand &>(*Operands[3]).isReg() && in shouldOmitCCOutOperand()
6710 static_cast<ARMOperand &>(*Operands[3]).getReg() == ARM::SP && in shouldOmitCCOutOperand()
6711 static_cast<ARMOperand &>(*Operands[1]).getReg() == 0 && in shouldOmitCCOutOperand()
6712 (static_cast<ARMOperand &>(*Operands[4]).isImm() || in shouldOmitCCOutOperand()
6713 (Operands.size() == 6 && in shouldOmitCCOutOperand()
6714 static_cast<ARMOperand &>(*Operands[5]).isImm()))) { in shouldOmitCCOutOperand()
6717 (static_cast<ARMOperand &>(*Operands[4]).isT2SOImm() || in shouldOmitCCOutOperand()
6718 static_cast<ARMOperand &>(*Operands[4]).isT2SOImmNeg()))); in shouldOmitCCOutOperand()
6724 (Operands.size() == 5) && in shouldOmitCCOutOperand()
6725 static_cast<ARMOperand &>(*Operands[3]).isReg() && in shouldOmitCCOutOperand()
6726 static_cast<ARMOperand &>(*Operands[3]).getReg() != ARM::SP && in shouldOmitCCOutOperand()
6727 static_cast<ARMOperand &>(*Operands[3]).getReg() != ARM::PC && in shouldOmitCCOutOperand()
6728 static_cast<ARMOperand &>(*Operands[1]).getReg() == 0 && in shouldOmitCCOutOperand()
6729 static_cast<ARMOperand &>(*Operands[4]).isImm()) { in shouldOmitCCOutOperand()
6730 const ARMOperand &IMM = static_cast<ARMOperand &>(*Operands[4]); in shouldOmitCCOutOperand()
6737 isARMLowRegister(static_cast<ARMOperand &>(*Operands[3]).getReg())) in shouldOmitCCOutOperand()
6746 OperandVector &Operands) { in shouldOmitPredicateOperand() argument
6751 (static_cast<ARMOperand &>(*Operands[2]).getToken() == ".f32" || in shouldOmitPredicateOperand()
6752 static_cast<ARMOperand &>(*Operands[2]).getToken() == ".f16")) { in shouldOmitPredicateOperand()
6753 if (static_cast<ARMOperand &>(*Operands[3]).isToken() && in shouldOmitPredicateOperand()
6754 (static_cast<ARMOperand &>(*Operands[3]).getToken() == ".f32" || in shouldOmitPredicateOperand()
6755 static_cast<ARMOperand &>(*Operands[3]).getToken() == ".f16")) in shouldOmitPredicateOperand()
6758 if (static_cast<ARMOperand &>(*Operands[RegIdx]).isReg() && in shouldOmitPredicateOperand()
6760 static_cast<ARMOperand &>(*Operands[RegIdx]).getReg()) || in shouldOmitPredicateOperand()
6762 static_cast<ARMOperand &>(*Operands[RegIdx]).getReg()))) in shouldOmitPredicateOperand()
6769 OperandVector &Operands) { in shouldOmitVectorPredicateOperand() argument
6770 if (!hasMVE() || Operands.size() < 3) in shouldOmitVectorPredicateOperand()
6783 for (auto &Operand : Operands) { in shouldOmitVectorPredicateOperand()
6795 for (auto &Operand : Operands) { in shouldOmitVectorPredicateOperand()
6838 OperandVector &Operands) { in fixupGNULDRDAlias() argument
6841 if (Operands.size() < 4) in fixupGNULDRDAlias()
6844 ARMOperand &Op2 = static_cast<ARMOperand &>(*Operands[2]); in fixupGNULDRDAlias()
6845 ARMOperand &Op3 = static_cast<ARMOperand &>(*Operands[3]); in fixupGNULDRDAlias()
6869 Operands.insert( in fixupGNULDRDAlias()
6870 Operands.begin() + 3, in fixupGNULDRDAlias()
6880 OperandVector &Operands) { in CDEConvertDualRegOperand() argument
6886 if (Operands.size() <= 3 + NumPredOps) in CDEConvertDualRegOperand()
6892 const MCParsedAsmOperand &Op2 = *Operands[2 + NumPredOps]; in CDEConvertDualRegOperand()
6927 const MCParsedAsmOperand &Op3 = *Operands[3 + NumPredOps]; in CDEConvertDualRegOperand()
6931 Operands.erase(Operands.begin() + 3 + NumPredOps); in CDEConvertDualRegOperand()
6932 Operands[2 + NumPredOps] = in CDEConvertDualRegOperand()
6939 SMLoc NameLoc, OperandVector &Operands) { in ParseInstruction() argument
6979 Operands.push_back(ARMOperand::CreateToken(Mnemonic, NameLoc)); in ParseInstruction()
7011 Operands.push_back(ARMOperand::CreateITMask(Mask, Loc)); in ParseInstruction()
7051 Operands.push_back(ARMOperand::CreateCCOut(CarrySetting ? ARM::CPSR : 0, in ParseInstruction()
7059 Operands.push_back(ARMOperand::CreateCondCode( in ParseInstruction()
7076 Operands.push_back(ARMOperand::CreateVPTPred( in ParseInstruction()
7082 Operands.push_back(ARMOperand::CreateImm( in ParseInstruction()
7113 Operands.push_back(ARMOperand::CreateToken(ExtraToken, Loc)); in ParseInstruction()
7120 if (parseOperand(Operands, Mnemonic)) { in ParseInstruction()
7126 if (parseOperand(Operands, Mnemonic)) { in ParseInstruction()
7135 tryConvertingToTwoOperandForm(Mnemonic, CarrySetting, Operands); in ParseInstruction()
7146 bool GotError = CDEConvertDualRegOperand(Mnemonic, Operands); in ParseInstruction()
7159 if (!CarrySetting && shouldOmitCCOutOperand(Mnemonic, Operands)) in ParseInstruction()
7160 Operands.erase(Operands.begin() + 1); in ParseInstruction()
7167 shouldOmitPredicateOperand(Mnemonic, Operands)) in ParseInstruction()
7168 Operands.erase(Operands.begin() + 1); in ParseInstruction()
7172 if (!shouldOmitVectorPredicateOperand(Mnemonic, Operands) && in ParseInstruction()
7177 Operands.erase(Operands.begin() + 1); in ParseInstruction()
7178 Operands.erase(Operands.begin()); in ParseInstruction()
7182 Operands.insert(Operands.begin(), in ParseInstruction()
7184 Operands.insert(Operands.begin(), in ParseInstruction()
7187 !shouldOmitVectorPredicateOperand(Mnemonic, Operands)) { in ParseInstruction()
7192 Operands.erase(Operands.begin() + 1); in ParseInstruction()
7193 Operands.erase(Operands.begin()); in ParseInstruction()
7197 Operands.insert(Operands.begin(), in ParseInstruction()
7199 Operands.insert(Operands.begin(), in ParseInstruction()
7202 !shouldOmitVectorPredicateOperand(Mnemonic, Operands)) { in ParseInstruction()
7206 Operands.erase(Operands.begin() + 1); in ParseInstruction()
7207 Operands.erase(Operands.begin()); in ParseInstruction()
7209 Operands.insert(Operands.begin(), in ParseInstruction()
7222 if (!shouldOmitVectorPredicateOperand(Mnemonic, Operands)) { in ParseInstruction()
7229 if (Mnemonic.starts_with("vcvtt") && Operands.size() >= 4) { in ParseInstruction()
7230 auto Sz1 = static_cast<ARMOperand &>(*Operands[2]); in ParseInstruction()
7231 auto Sz2 = static_cast<ARMOperand &>(*Operands[3]); in ParseInstruction()
7234 Operands.erase(Operands.begin()); in ParseInstruction()
7239 Operands.insert(Operands.begin(), in ParseInstruction()
7243 Operands.erase(Operands.begin() + 1); in ParseInstruction()
7246 Operands.insert(Operands.begin() + 1, in ParseInstruction()
7254 if (shouldOmitVectorPredicateOperand(Mnemonic, Operands)) { in ParseInstruction()
7256 Operands.erase(Operands.begin() + 2); in ParseInstruction()
7258 Operands.erase(Operands.begin() + 1); in ParseInstruction()
7260 Operands.erase(Operands.begin() + 1); in ParseInstruction()
7267 for (unsigned I = 1; I < Operands.size(); ++I) in ParseInstruction()
7268 if (static_cast<ARMOperand &>(*Operands[I]).isVPTPred()) in ParseInstruction()
7279 Operands.erase(Operands.begin()); in ParseInstruction()
7280 Operands.insert(Operands.begin(), in ParseInstruction()
7290 if (!isThumb() && Mnemonic == "blx" && Operands.size() == 3 && in ParseInstruction()
7291 static_cast<ARMOperand &>(*Operands[2]).isImm()) in ParseInstruction()
7292 Operands.erase(Operands.begin() + 1); in ParseInstruction()
7301 if (!isThumb() && Operands.size() > 4 && in ParseInstruction()
7306 ARMOperand &Op1 = static_cast<ARMOperand &>(*Operands[Idx]); in ParseInstruction()
7307 ARMOperand &Op2 = static_cast<ARMOperand &>(*Operands[Idx + 1]); in ParseInstruction()
7326 Operands[Idx] = in ParseInstruction()
7328 Operands.erase(Operands.begin() + Idx + 1); in ParseInstruction()
7333 fixupGNULDRDAlias(Mnemonic, Operands); in ParseInstruction()
7340 if (isThumbTwo() && Mnemonic == "sub" && Operands.size() == 6 && in ParseInstruction()
7341 static_cast<ARMOperand &>(*Operands[3]).isReg() && in ParseInstruction()
7342 static_cast<ARMOperand &>(*Operands[3]).getReg() == ARM::PC && in ParseInstruction()
7343 static_cast<ARMOperand &>(*Operands[4]).isReg() && in ParseInstruction()
7344 static_cast<ARMOperand &>(*Operands[4]).getReg() == ARM::LR && in ParseInstruction()
7345 static_cast<ARMOperand &>(*Operands[5]).isImm()) { in ParseInstruction()
7346 Operands.front() = ARMOperand::CreateToken(Name, NameLoc); in ParseInstruction()
7347 Operands.erase(Operands.begin() + 1); in ParseInstruction()
7393 const OperandVector &Operands, in validatetLDMRegList() argument
7395 const ARMOperand &Op = static_cast<const ARMOperand &>(*Operands[ListNo]); in validatetLDMRegList()
7403 return Error(Operands[ListNo + HasWritebackToken]->getStartLoc(), in validatetLDMRegList()
7406 return Error(Operands[ListNo + HasWritebackToken]->getStartLoc(), in validatetLDMRegList()
7412 const OperandVector &Operands, in validatetSTMRegList() argument
7414 const ARMOperand &Op = static_cast<const ARMOperand &>(*Operands[ListNo]); in validatetSTMRegList()
7421 return Error(Operands[ListNo + HasWritebackToken]->getStartLoc(), in validatetSTMRegList()
7424 return Error(Operands[ListNo + HasWritebackToken]->getStartLoc(), in validatetSTMRegList()
7427 return Error(Operands[ListNo + HasWritebackToken]->getStartLoc(), in validatetSTMRegList()
7433 const OperandVector &Operands, in validateLDRDSTRD() argument
7442 return Error(Operands[3]->getStartLoc(), in validateLDRDSTRD()
7447 return Error(Operands[3]->getStartLoc(), in validateLDRDSTRD()
7453 return Error(Operands[3]->getStartLoc(), in validateLDRDSTRD()
7456 return Error(Operands[3]->getStartLoc(), in validateLDRDSTRD()
7466 return Error(Operands[3]->getStartLoc(), in validateLDRDSTRD()
7475 return Error(Operands[3]->getStartLoc(), in validateLDRDSTRD()
7479 return Error(Operands[3]->getStartLoc(), in validateLDRDSTRD()
7517 const OperandVector &Operands) { in validateInstruction() argument
7519 SMLoc Loc = Operands[0]->getStartLoc(); in validateInstruction()
7533 for (unsigned I = 1; I < Operands.size(); ++I) in validateInstruction()
7534 if (static_cast<ARMOperand &>(*Operands[I]).isCondCode()) in validateInstruction()
7535 CondLoc = Operands[I]->getStartLoc(); in validateInstruction()
7580 for (unsigned I = 1; I < Operands.size(); ++I) in validateInstruction()
7581 if (static_cast<ARMOperand &>(*Operands[I]).isVPTPred()) in validateInstruction()
7582 PredLoc = Operands[I]->getStartLoc(); in validateInstruction()
7611 if (validateLDRDSTRD(Inst, Operands, /*Load*/true, /*ARMMode*/true, in validateInstruction()
7617 if (validateLDRDSTRD(Inst, Operands, /*Load*/true, /*ARMMode*/true, in validateInstruction()
7622 if (validateLDRDSTRD(Inst, Operands, /*Load*/true, /*ARMMode*/false, in validateInstruction()
7628 if (validateLDRDSTRD(Inst, Operands, /*Load*/true, /*ARMMode*/false, in validateInstruction()
7636 return Error(Operands[2]->getStartLoc(), in validateInstruction()
7641 if (validateLDRDSTRD(Inst, Operands, /*Load*/false, /*ARMMode*/true, in validateInstruction()
7647 if (validateLDRDSTRD(Inst, Operands, /*Load*/false, /*ARMMode*/true, in validateInstruction()
7653 if (validateLDRDSTRD(Inst, Operands, /*Load*/false, /*ARMMode*/false, in validateInstruction()
7678 return Error(Operands[3]->getStartLoc(), in validateInstruction()
7691 return Error(Operands[3]->getStartLoc(), in validateInstruction()
7697 return Error(Operands[5]->getStartLoc(), in validateInstruction()
7703 return Error(Operands[3]->getStartLoc(), in validateInstruction()
7722 return Error(Operands[5]->getStartLoc(), in validateInstruction()
7728 return Error(Operands[5]->getStartLoc(), in validateInstruction()
7732 return Error(Operands[3]->getStartLoc(), in validateInstruction()
7750 return Error(Operands[5]->getStartLoc(), in validateInstruction()
7756 return Error(Operands[5]->getStartLoc(), in validateInstruction()
7760 return Error(Operands[3]->getStartLoc(), in validateInstruction()
7773 return Error(Operands[5]->getStartLoc(), in validateInstruction()
7778 return Error(Operands[5]->getStartLoc(), in validateInstruction()
7782 return Error(Operands[3]->getStartLoc(), in validateInstruction()
7795 return Error(Operands[5]->getStartLoc(), in validateInstruction()
7800 return Error(Operands[5]->getStartLoc(), in validateInstruction()
7804 return Error(Operands[3]->getStartLoc(), in validateInstruction()
7839 return Error(Operands[3]->getStartLoc(), in validateInstruction()
7883 return Error(Operands[3]->getStartLoc(), in validateInstruction()
7899 return Error(Operands[5]->getStartLoc(), in validateInstruction()
7913 (static_cast<ARMOperand &>(*Operands[3]).isToken() && in validateInstruction()
7914 static_cast<ARMOperand &>(*Operands[3]).getToken() == "!"); in validateInstruction()
7917 return Error(Operands[3 + HasWritebackToken]->getStartLoc(), in validateInstruction()
7921 return Error(Operands[2]->getStartLoc(), in validateInstruction()
7926 return Error(Operands[3]->getStartLoc(), in validateInstruction()
7930 if (validatetLDMRegList(Inst, Operands, 3)) in validateInstruction()
7943 return Error(Operands.back()->getStartLoc(), in validateInstruction()
7948 if (validatetLDMRegList(Inst, Operands, 3)) in validateInstruction()
7953 if (validatetSTMRegList(Inst, Operands, 3)) in validateInstruction()
7961 return Error(Operands.back()->getStartLoc(), in validateInstruction()
7965 if (validatetLDMRegList(Inst, Operands, 3)) in validateInstruction()
7968 if (validatetSTMRegList(Inst, Operands, 3)) in validateInstruction()
7978 return Error(Operands[4]->getStartLoc(), in validateInstruction()
7986 return Error(Operands[2]->getStartLoc(), in validateInstruction()
7997 if (Operands.size() == 6 && (((ARMOperand &)*Operands[3]).getReg() != in validateInstruction()
7998 ((ARMOperand &)*Operands[5]).getReg()) && in validateInstruction()
7999 (((ARMOperand &)*Operands[3]).getReg() != in validateInstruction()
8000 ((ARMOperand &)*Operands[4]).getReg())) { in validateInstruction()
8001 return Error(Operands[3]->getStartLoc(), in validateInstruction()
8013 return Error(Operands[2]->getStartLoc(), in validateInstruction()
8015 if (validatetLDMRegList(Inst, Operands, 2, !isMClass())) in validateInstruction()
8023 return Error(Operands[2]->getStartLoc(), in validateInstruction()
8025 if (validatetSTMRegList(Inst, Operands, 2)) in validateInstruction()
8034 return Error(Operands[4]->getStartLoc(), in validateInstruction()
8040 return Error(Operands[4]->getStartLoc(), in validateInstruction()
8044 if (validatetSTMRegList(Inst, Operands, 4)) in validateInstruction()
8053 return Error(Operands[4]->getStartLoc(), in validateInstruction()
8064 return Error(Operands[4]->getStartLoc(), in validateInstruction()
8070 if (!(static_cast<ARMOperand &>(*Operands[2])).isSignedOffset<11, 1>()) in validateInstruction()
8071 return Error(Operands[2]->getStartLoc(), "branch target out of range"); in validateInstruction()
8074 int op = (Operands[2]->isImm()) ? 2 : 3; in validateInstruction()
8075 ARMOperand &Operand = static_cast<ARMOperand &>(*Operands[op]); in validateInstruction()
8079 return Error(Operands[op]->getStartLoc(), "branch target out of range"); in validateInstruction()
8084 if (!static_cast<ARMOperand &>(*Operands[2]).isSignedOffset<8, 1>()) in validateInstruction()
8085 return Error(Operands[2]->getStartLoc(), "branch target out of range"); in validateInstruction()
8088 int Op = (Operands[2]->isImm()) ? 2 : 3; in validateInstruction()
8089 if (!static_cast<ARMOperand &>(*Operands[Op]).isSignedOffset<20, 1>()) in validateInstruction()
8090 return Error(Operands[Op]->getStartLoc(), "branch target out of range"); in validateInstruction()
8095 if (!static_cast<ARMOperand &>(*Operands[2]).isUnsignedOffset<6, 1>()) in validateInstruction()
8096 return Error(Operands[2]->getStartLoc(), "branch target out of range"); in validateInstruction()
8110 int i = (Operands[3]->isImm()) ? 3 : 4; in validateInstruction()
8111 ARMOperand &Op = static_cast<ARMOperand &>(*Operands[i]); in validateInstruction()
8125 MCParsedAsmOperand &Op = *Operands[4]; in validateInstruction()
8133 MCParsedAsmOperand &Op = *Operands[2]; in validateInstruction()
8147 return Error(Operands[1]->getStartLoc(), "instruction 'esb' is not " in validateInstruction()
8151 return Error(Operands[1]->getStartLoc(), "instruction 'csdb' is not " in validateInstruction()
8160 if (!static_cast<ARMOperand &>(*Operands[2]).isUnsignedOffset<4, 1>() || in validateInstruction()
8162 return Error(Operands[2]->getStartLoc(), in validateInstruction()
8166 if (!static_cast<ARMOperand &>(*Operands[3]).isSignedOffset<16, 1>()) in validateInstruction()
8167 return Error(Operands[3]->getStartLoc(), in validateInstruction()
8170 if (!static_cast<ARMOperand &>(*Operands[3]).isSignedOffset<18, 1>()) in validateInstruction()
8171 return Error(Operands[3]->getStartLoc(), in validateInstruction()
8177 if (!static_cast<ARMOperand &>(*Operands[1]).isUnsignedOffset<4, 1>() || in validateInstruction()
8179 return Error(Operands[1]->getStartLoc(), in validateInstruction()
8182 if (!static_cast<ARMOperand &>(*Operands[2]).isSignedOffset<16, 1>()) in validateInstruction()
8183 return Error(Operands[2]->getStartLoc(), in validateInstruction()
8194 Operands[3]->getStartLoc(), in validateInstruction()
8204 return Error(Operands[2]->getStartLoc(), in validateInstruction()
8222 return Error(Operands[1]->getStartLoc(), in validateInstruction()
8226 return Error(Operands[1]->getStartLoc(), in validateInstruction()
8236 return Error(Operands[5]->getStartLoc(), in validateInstruction()
8245 return Error(Operands[3]->getStartLoc(), in validateInstruction()
8251 ARMOperand &Op = static_cast<ARMOperand&>(*Operands[3]); in validateInstruction()
8254 return Error(Operands[3]->getStartLoc(), in validateInstruction()
8265 if (Operands[3]->getReg() == Operands[4]->getReg()) { in validateInstruction()
8266 return Error (Operands[3]->getStartLoc(), in validateInstruction()
8269 if (Operands[3]->getReg() == Operands[5]->getReg()) { in validateInstruction()
8270 return Error (Operands[3]->getStartLoc(), in validateInstruction()
8280 if (Operands[3]->getReg() == Operands[4]->getReg()) { in validateInstruction()
8281 return Error (Operands[3]->getStartLoc(), in validateInstruction()
8289 if (Operands[3]->getReg() == Operands[5]->getReg()) { in validateInstruction()
8290 return Error (Operands[3]->getStartLoc(), in validateInstruction()
8296 if (Operands[4]->getReg() != Operands[6]->getReg()) in validateInstruction()
8297 return Error (Operands[4]->getStartLoc(), "Q-registers must be the same"); in validateInstruction()
8298 if (static_cast<ARMOperand &>(*Operands[5]).getVectorIndex() != in validateInstruction()
8299 static_cast<ARMOperand &>(*Operands[7]).getVectorIndex() + 2) in validateInstruction()
8300 return Error (Operands[5]->getStartLoc(), "Q-register indexes must be 2 and 0 or 3 and 1"); in validateInstruction()
8304 if (Operands[2]->getReg() != Operands[4]->getReg()) in validateInstruction()
8305 return Error (Operands[2]->getStartLoc(), "Q-registers must be the same"); in validateInstruction()
8306 if (static_cast<ARMOperand &>(*Operands[3]).getVectorIndex() != in validateInstruction()
8307 static_cast<ARMOperand &>(*Operands[5]).getVectorIndex() + 2) in validateInstruction()
8308 return Error (Operands[3]->getStartLoc(), "Q-register indexes must be 2 and 0 or 3 and 1"); in validateInstruction()
8313 if (Operands[2]->getReg() == Operands[3]->getReg()) { in validateInstruction()
8314 return Error(Operands[2]->getStartLoc(), in validateInstruction()
8388 return Error(Operands[1]->getStartLoc(), in validateInstruction()
8391 return Error(Operands[1]->getStartLoc(), in validateInstruction()
8451 return Error(Operands[2]->getStartLoc(), in validateInstruction()
8717 const OperandVector &Operands, in processInstruction() argument
8722 for (auto &Op : Operands) { in processInstruction()
9039 static_cast<ARMOperand &>(*Operands[4]) : in processInstruction()
9040 static_cast<ARMOperand &>(*Operands[3])); in processInstruction()
10402 if (static_cast<ARMOperand &>(*Operands[0]).getToken() == "pop" && in processInstruction()
10420 if (static_cast<ARMOperand &>(*Operands[0]).getToken() == "push" && in processInstruction()
10439 const StringRef Token = static_cast<ARMOperand &>(*Operands[0]).getToken(); in processInstruction()
10467 (unsigned)Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) { in processInstruction()
10477 if ((unsigned)Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) { in processInstruction()
10597 (static_cast<ARMOperand &>(*Operands[3]).isToken() && in processInstruction()
10598 static_cast<ARMOperand &>(*Operands[3]).getToken() == "!"); in processInstruction()
11040 unsigned ARMAsmParser::MatchInstruction(OperandVector &Operands, MCInst &Inst, in MatchInstruction() argument
11047 return MatchInstructionImpl(Operands, Inst, &NearMisses, MatchingInlineAsm); in MatchInstruction()
11053 if (MatchInstructionImpl(Operands, Inst, nullptr, MatchingInlineAsm) == in MatchInstruction()
11079 MatchInstructionImpl(Operands, Inst, &NearMisses, MatchingInlineAsm); in MatchInstruction()
11106 if (MatchInstructionImpl(Operands, Inst, nullptr, MatchingInlineAsm) == in MatchInstruction()
11130 OperandVector &Operands, in MatchAndEmitInstruction() argument
11138 MatchResult = MatchInstruction(Operands, Inst, NearMisses, MatchingInlineAsm, in MatchAndEmitInstruction()
11149 if (validateInstruction(Inst, Operands)) { in MatchAndEmitInstruction()
11162 while (processInstruction(Inst, Operands, Out)) in MatchAndEmitInstruction()
11189 ReportNearMisses(NearMisses, IDLoc, Operands); in MatchAndEmitInstruction()
11194 ((ARMOperand &)*Operands[0]).getToken(), FBS); in MatchAndEmitInstruction()
11196 ((ARMOperand &)*Operands[0]).getLocRange()); in MatchAndEmitInstruction()
11908 SmallVector<std::unique_ptr<MCParsedAsmOperand>, 1> Operands; in parseDirectiveRegSave() local
11911 if (parseRegisterList(Operands, true, true) || parseEOL()) in parseDirectiveRegSave()
11913 ARMOperand &Op = (ARMOperand &)*Operands[0]; in parseDirectiveRegSave()
12257 SmallVector<std::unique_ptr<MCParsedAsmOperand>, 1> Operands; in parseDirectiveSEHSaveRegs() local
12259 if (parseRegisterList(Operands) || parseEOL()) in parseDirectiveSEHSaveRegs()
12261 ARMOperand &Op = (ARMOperand &)*Operands[0]; in parseDirectiveSEHSaveRegs()
12299 SmallVector<std::unique_ptr<MCParsedAsmOperand>, 1> Operands; in parseDirectiveSEHSaveFRegs() local
12301 if (parseRegisterList(Operands) || parseEOL()) in parseDirectiveSEHSaveFRegs()
12303 ARMOperand &Op = (ARMOperand &)*Operands[0]; in parseDirectiveSEHSaveFRegs()
12455 SMLoc IDLoc, OperandVector &Operands) { in FilterNearMisses() argument
12478 ((ARMOperand &)*Operands[I.getOperandIndex()]).getStartLoc(); in FilterNearMisses()
12592 SMLoc EndLoc = ((ARMOperand &)*Operands.back()).getEndLoc(); in FilterNearMisses()
12608 SMLoc IDLoc, OperandVector &Operands) { in ReportNearMisses() argument
12610 FilterNearMisses(NearMisses, Messages, IDLoc, Operands); in ReportNearMisses()