Lines Matching refs:addPass

419     addPass(createLowerAtomicPass());  in addIRPasses()
421 addPass(createAtomicExpandPass()); in addIRPasses()
427 addPass(createCFGSimplificationPass( in addIRPasses()
434 addPass(createMVEGatherScatterLoweringPass()); in addIRPasses()
435 addPass(createMVELaneInterleavingPass()); in addIRPasses()
441 addPass(createARMParallelDSPPass()); in addIRPasses()
445 addPass(createComplexDeinterleavingPass(TM)); in addIRPasses()
449 addPass(createInterleavedAccessPass()); in addIRPasses()
453 addPass(createCFGuardCheckPass()); in addIRPasses()
456 addPass(createJMCInstrumenterPass()); in addIRPasses()
461 addPass(createTypePromotionLegacyPass()); in addCodeGenPrepare()
482 addPass(createGlobalMergePass(TM, 127, OnlyOptimizeForSize, in addPreISel()
487 addPass(createHardwareLoopsLegacyPass()); in addPreISel()
488 addPass(createMVETailPredicationPass()); in addPreISel()
496 addPass(createBarrierNoopPass()); in addPreISel()
503 addPass(createARMISelDag(getARMTargetMachine(), getOptLevel())); in addInstSelector()
508 addPass(new IRTranslator(getOptLevel())); in addIRTranslator()
513 addPass(new Legalizer()); in addLegalizeMachineIR()
518 addPass(new RegBankSelect()); in addRegBankSelect()
523 addPass(new InstructionSelect(getOptLevel())); in addGlobalInstructionSelect()
530 addPass(&MachinePipelinerID); in addPreRegAlloc()
532 addPass(createMVETPAndVPTOptimisationsPass()); in addPreRegAlloc()
534 addPass(createMLxExpansionPass()); in addPreRegAlloc()
537 addPass(createARMLoadStoreOptimizationPass(/* pre-register alloc */ true)); in addPreRegAlloc()
540 addPass(createA15SDOptimizerPass()); in addPreRegAlloc()
547 addPass(createARMLoadStoreOptimizationPass()); in addPreSched2()
549 addPass(new ARMExecutionDomainFix()); in addPreSched2()
550 addPass(createBreakFalseDeps()); in addPreSched2()
555 addPass(createARMExpandPseudoPass()); in addPreSched2()
561 addPass(createThumb2SizeReductionPass([this](const Function &F) { in addPreSched2()
566 addPass(createIfConverter([](const MachineFunction &MF) { in addPreSched2()
570 addPass(createThumb2ITBlockPass()); in addPreSched2()
575 addPass(&PostMachineSchedulerID); in addPreSched2()
576 addPass(&PostRASchedulerID); in addPreSched2()
579 addPass(createMVEVPTBlockPass()); in addPreSched2()
580 addPass(createARMIndirectThunks()); in addPreSched2()
581 addPass(createARMSLSHardeningPass()); in addPreSched2()
585 addPass(createThumb2SizeReductionPass()); in addPreEmitPass()
588 addPass(createUnpackMachineBundles([](const MachineFunction &MF) { in addPreEmitPass()
594 addPass(createARMBlockPlacementPass()); in addPreEmitPass()
595 addPass(createARMOptimizeBarriersPass()); in addPreEmitPass()
603 addPass(createARMFixCortexA57AES1742098Pass()); in addPreEmitPass2()
606 addPass(createARMBranchTargetsPass()); in addPreEmitPass2()
610 addPass(createARMConstantIslandPass()); in addPreEmitPass2()
614 addPass(createARMLowOverheadLoopsPass()); in addPreEmitPass2()
618 addPass(createCFGuardLongjmpPass()); in addPreEmitPass2()
620 addPass(createEHContGuardCatchretPass()); in addPreEmitPass2()