142     const RegisterBank &RBGPR = getRegBank(ARM::GPRRegBankID);  in ARMRegisterBankInfo()  local
143     (void)RBGPR;  in ARMRegisterBankInfo()
144     assert(&ARM::GPRRegBank == &RBGPR && "The order in RegBanks is messed up");  in ARMRegisterBankInfo()
147     assert(RBGPR.covers(*TRI.getRegClass(ARM::GPRRegClassID)) &&  in ARMRegisterBankInfo()
149     assert(RBGPR.covers(*TRI.getRegClass(ARM::GPRwithAPSRRegClassID)) &&  in ARMRegisterBankInfo()
151     assert(RBGPR.covers(*TRI.getRegClass(ARM::GPRnopcRegClassID)) &&  in ARMRegisterBankInfo()
153     assert(RBGPR.covers(*TRI.getRegClass(ARM::rGPRRegClassID)) &&  in ARMRegisterBankInfo()
155     assert(RBGPR.covers(*TRI.getRegClass(ARM::tGPRRegClassID)) &&  in ARMRegisterBankInfo()
157     assert(RBGPR.covers(*TRI.getRegClass(ARM::tcGPRRegClassID)) &&  in ARMRegisterBankInfo()
159     assert(RBGPR.covers(*TRI.getRegClass(ARM::GPRnoip_and_tcGPRRegClassID)) &&  in ARMRegisterBankInfo()
161     assert(RBGPR.covers(*TRI.getRegClass(  in ARMRegisterBankInfo()
164     assert(RBGPR.covers(*TRI.getRegClass(ARM::tGPROdd_and_tcGPRRegClassID)) &&  in ARMRegisterBankInfo()
166     assert(getMaximumSize(RBGPR.getID()) == 32 &&  in ARMRegisterBankInfo()