180         ArrayRef<std::pair<unsigned, bool>> Regs,
186         ArrayRef<std::pair<unsigned, bool>> Regs,
616 static bool ContainsReg(const ArrayRef<std::pair<unsigned, bool>> &Regs,  in ContainsReg()  argument
618   for (const std::pair<unsigned, bool> &R : Regs)  in ContainsReg()
631     ArrayRef<std::pair<unsigned, bool>> Regs,  in CreateLoadStoreMulti()  argument
633   unsigned NumRegs = Regs.size();  in CreateLoadStoreMulti()
647   if (isThumb1 && ContainsReg(Regs, Base)) {  in CreateLoadStoreMulti()
687       NewBase = Regs[NumRegs-1].first;  in CreateLoadStoreMulti()
695         for (const std::pair<unsigned, bool> &R : Regs)  in CreateLoadStoreMulti()
729       (!isi32Store(Opcode) || !ContainsReg(Regs, Base));  in CreateLoadStoreMulti()
803       assert(!(ContainsReg(Regs, Base)) && "Thumb1 can't LDM ! with Base in Regs");  in CreateLoadStoreMulti()
826   for (const std::pair<unsigned, bool> &R : Regs)  in CreateLoadStoreMulti()
838     ArrayRef<std::pair<unsigned, bool>> Regs,  in CreateLoadStoreDouble()  argument
844   assert(Regs.size() == 2);  in CreateLoadStoreDouble()
848     MIB.addReg(Regs[0].first, RegState::Define)  in CreateLoadStoreDouble()
849        .addReg(Regs[1].first, RegState::Define);  in CreateLoadStoreDouble()
851     MIB.addReg(Regs[0].first, getKillRegState(Regs[0].second))  in CreateLoadStoreDouble()
852        .addReg(Regs[1].first, getKillRegState(Regs[1].second));  in CreateLoadStoreDouble()
864   SmallVector<std::pair<unsigned, bool>, 8> Regs;  in MergeOpsUpdate()  local
875     Regs.push_back(std::make_pair(Reg, IsKill));  in MergeOpsUpdate()
913                                    Opcode, Pred, PredReg, DL, Regs,  in MergeOpsUpdate()
917                                   Opcode, Pred, PredReg, DL, Regs, Cand.Instrs);  in MergeOpsUpdate()