175                            ARMCC::CondCodes Pred, unsigned PredReg);
179         ARMCC::CondCodes Pred, unsigned PredReg, const DebugLoc &DL,
185         ARMCC::CondCodes Pred, unsigned PredReg, const DebugLoc &DL,
490                                         unsigned PredReg) {  in UpdateBaseRegUses()  argument
559           .addReg(PredReg);  in UpdateBaseRegUses()
580         .addReg(PredReg);  in UpdateBaseRegUses()
630     ARMCC::CondCodes Pred, unsigned PredReg, const DebugLoc &DL,  in CreateLoadStoreMulti()  argument
750               .add(predOps(Pred, PredReg));  in CreateLoadStoreMulti()
761             .add(predOps(Pred, PredReg));  in CreateLoadStoreMulti()
767             .add(predOps(Pred, PredReg));  in CreateLoadStoreMulti()
772           .add(predOps(Pred, PredReg))  in CreateLoadStoreMulti()
817       UpdateBaseRegUses(MBB, InsertBefore, DL, Base, NumRegs, Pred, PredReg);  in CreateLoadStoreMulti()
824   MIB.addImm(Pred).addReg(PredReg);  in CreateLoadStoreMulti()
837     ARMCC::CondCodes Pred, unsigned PredReg, const DebugLoc &DL,  in CreateLoadStoreDouble()  argument
854   MIB.addReg(Base).addImm(Offset).addImm(Pred).addReg(PredReg);  in CreateLoadStoreDouble()
907   Register PredReg;  in MergeOpsUpdate()  local
908   ARMCC::CondCodes Pred = getInstrPredicate(*First, PredReg);  in MergeOpsUpdate()
913                                    Opcode, Pred, PredReg, DL, Regs,  in MergeOpsUpdate()
917                                   Opcode, Pred, PredReg, DL, Regs, Cand.Instrs);  in MergeOpsUpdate()
1191                                   ARMCC::CondCodes Pred, Register PredReg) {  in isIncrementOrDecrement()  argument
1212       MIPredReg != PredReg)  in isIncrementOrDecrement()
1223                  ARMCC::CondCodes Pred, Register PredReg, int &Offset) {  in findIncDecBefore()  argument
1236   Offset = isIncrementOrDecrement(*PrevMBBI, Reg, Pred, PredReg);  in findIncDecBefore()
1243                 ARMCC::CondCodes Pred, Register PredReg, int &Offset,  in findIncDecAfter()  argument
1256     unsigned Off = isIncrementOrDecrement(*NextMBBI, Reg, Pred, PredReg);  in findIncDecAfter()
1296   Register PredReg;  in MergeBaseUpdateLSMultiple()  local
1297   ARMCC::CondCodes Pred = getInstrPredicate(*MI, PredReg);  in MergeBaseUpdateLSMultiple()
1312     = findIncDecBefore(MBBI, Base, Pred, PredReg, Offset);  in MergeBaseUpdateLSMultiple()
1319     MergeInstr = findIncDecAfter(MBBI, Base, Pred, PredReg, Offset, TRI);  in MergeBaseUpdateLSMultiple()
1352     .addImm(Pred).addReg(PredReg);  in MergeBaseUpdateLSMultiple()
1492   Register PredReg;  in MergeBaseUpdateLoadStore()  local
1493   ARMCC::CondCodes Pred = getInstrPredicate(*MI, PredReg);  in MergeBaseUpdateLoadStore()
1499     = findIncDecBefore(MBBI, Base, Pred, PredReg, Offset);  in MergeBaseUpdateLoadStore()
1506     MergeInstr = findIncDecAfter(MBBI, Base, Pred, PredReg, Offset, TRI);  in MergeBaseUpdateLoadStore()
1534                    .addReg(PredReg)  in MergeBaseUpdateLoadStore()
1550                 .addReg(PredReg)  in MergeBaseUpdateLoadStore()
1562                 .add(predOps(Pred, PredReg))  in MergeBaseUpdateLoadStore()
1574               .add(predOps(Pred, PredReg))  in MergeBaseUpdateLoadStore()
1592                      .add(predOps(Pred, PredReg))  in MergeBaseUpdateLoadStore()
1602                      .add(predOps(Pred, PredReg))  in MergeBaseUpdateLoadStore()
1630   Register PredReg;  in MergeBaseUpdateLSDouble()  local
1631   ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg);  in MergeBaseUpdateLSDouble()
1636                                                             PredReg, Offset);  in MergeBaseUpdateLSDouble()
1641     MergeInstr = findIncDecAfter(MBBI, Base, Pred, PredReg, Offset, TRI);  in MergeBaseUpdateLSDouble()
1660      .addImm(Offset).addImm(Pred).addReg(PredReg);  in MergeBaseUpdateLSDouble()
1737                           unsigned PredReg, const TargetInstrInfo *TII,  in InsertLDR_STR()  argument
1744     MIB.addImm(Offset).addImm(Pred).addReg(PredReg);  in InsertLDR_STR()
1753     MIB.addImm(Offset).addImm(Pred).addReg(PredReg);  in InsertLDR_STR()
1800   Register PredReg;  in FixInvalidRegPairOp()  local
1801   ARMCC::CondCodes Pred = getInstrPredicate(*MI, PredReg);  in FixInvalidRegPairOp()
1812         .addImm(Pred).addReg(PredReg)  in FixInvalidRegPairOp()
1820         .addImm(Pred).addReg(PredReg)  in FixInvalidRegPairOp()
1843                     false, BaseReg, false, BaseUndef, Pred, PredReg, TII, MI);  in FixInvalidRegPairOp()
1845                     false, BaseReg, BaseKill, BaseUndef, Pred, PredReg, TII,  in FixInvalidRegPairOp()
1859                     EvenUndef, BaseReg, false, BaseUndef, Pred, PredReg, TII,  in FixInvalidRegPairOp()
1862                     OddUndef, BaseReg, BaseKill, BaseUndef, Pred, PredReg, TII,  in FixInvalidRegPairOp()
1900       Register PredReg;  in LoadStoreMultipleOpti()  local
1901       ARMCC::CondCodes Pred = getInstrPredicate(*MBBI, PredReg);  in LoadStoreMultipleOpti()
2170                           Register &BaseReg, int &Offset, Register &PredReg,
2256     Register &PredReg, ARMCC::CondCodes &Pred, bool &isT2) {  in CanFormLdStDWord()  argument
2316   Pred = getInstrPredicate(*Op0, PredReg);  in CanFormLdStDWord()
2415         Register BaseReg, PredReg;  in RescheduleOps()  local
2423                                              Offset, PredReg, Pred, isT2)) {  in RescheduleOps()
2443             MIB.addImm(Offset).addImm(Pred).addReg(PredReg);  in RescheduleOps()
2457             MIB.addImm(Offset).addImm(Pred).addReg(PredReg);  in RescheduleOps()
2564       Register PredReg;  in RescheduleLoadStoreInstrs()  local
2565       if (getInstrPredicate(MI, PredReg) != ARMCC::AL)  in RescheduleLoadStoreInstrs()
3178     Register PredReg;  in DistributeIncrements()  local
3180         getInstrPredicate(*Increment, PredReg) != ARMCC::AL)  in DistributeIncrements()