1735                           bool RegDeadKill, bool RegUndef, unsigned BaseReg,  in InsertLDR_STR()  argument
1743       .addReg(BaseReg, getKillRegState(BaseKill)|getUndefRegState(BaseUndef));  in InsertLDR_STR()
1752       .addReg(BaseReg, getKillRegState(BaseKill)|getUndefRegState(BaseUndef));  in InsertLDR_STR()
1770   Register BaseReg = BaseOp.getReg();  in FixInvalidRegPairOp()  local
1778   bool Errata602117 = EvenReg == BaseReg &&  in FixInvalidRegPairOp()
1811         .addReg(BaseReg, getKillRegState(BaseKill))  in FixInvalidRegPairOp()
1819         .addReg(BaseReg, getKillRegState(BaseKill))  in FixInvalidRegPairOp()
1840     if (isLd && TRI->regsOverlap(EvenReg, BaseReg)) {  in FixInvalidRegPairOp()
1841       assert(!TRI->regsOverlap(OddReg, BaseReg));  in FixInvalidRegPairOp()
1843                     false, BaseReg, false, BaseUndef, Pred, PredReg, TII, MI);  in FixInvalidRegPairOp()
1845                     false, BaseReg, BaseKill, BaseUndef, Pred, PredReg, TII,  in FixInvalidRegPairOp()
1856       if (EvenReg == BaseReg)  in FixInvalidRegPairOp()
1859                     EvenUndef, BaseReg, false, BaseUndef, Pred, PredReg, TII,  in FixInvalidRegPairOp()
1862                     OddUndef, BaseReg, BaseKill, BaseUndef, Pred, PredReg, TII,  in FixInvalidRegPairOp()
2170                           Register &BaseReg, int &Offset, Register &PredReg,
2255     Register &FirstReg, Register &SecondReg, Register &BaseReg, int &Offset,  in CanFormLdStDWord()  argument
2315   BaseReg = Op0->getOperand(1).getReg();  in CanFormLdStDWord()
2415         Register BaseReg, PredReg;  in RescheduleOps()  local
2422                                              FirstReg, SecondReg, BaseReg,  in RescheduleOps()
2437               .addReg(BaseReg);  in RescheduleOps()
2451               .addReg(BaseReg);  in RescheduleOps()