178         int Offset, unsigned Base, bool BaseKill, unsigned Opcode,
184         int Offset, unsigned Base, bool BaseKill, unsigned Opcode,
629     int Offset, unsigned Base, bool BaseKill, unsigned Opcode,  in CreateLoadStoreMulti()  argument
703     int BaseOpc = isThumb2 ? (BaseKill && Base == ARM::SP ? ARM::t2ADDspImm  in CreateLoadStoreMulti()
715       BaseOpc = isThumb2 ? (BaseKill && Base == ARM::SP ? ARM::t2SUBspImm  in CreateLoadStoreMulti()
728     bool KillOldBase = BaseKill &&  in CreateLoadStoreMulti()
776     BaseKill = true; // New base is always killed straight away.  in CreateLoadStoreMulti()
795   if (isThumb1 && !SafeToClobberCPSR && Writeback && !BaseKill)  in CreateLoadStoreMulti()
812        .addReg(Base, getKillRegState(BaseKill));  in CreateLoadStoreMulti()
816     if (!BaseKill)  in CreateLoadStoreMulti()
821     MIB.addReg(Base, getKillRegState(BaseKill));  in CreateLoadStoreMulti()
836     int Offset, unsigned Base, bool BaseKill, unsigned Opcode,  in CreateLoadStoreDouble()  argument
906   bool BaseKill = LatestMI->killsRegister(Base);  in MergeOpsUpdate()  local
912     Merged = CreateLoadStoreDouble(MBB, InsertBefore, Offset, Base, BaseKill,  in MergeOpsUpdate()
916     Merged = CreateLoadStoreMulti(MBB, InsertBefore, Offset, Base, BaseKill,  in MergeOpsUpdate()
1295   bool BaseKill = BaseOP.isKill();  in MergeBaseUpdateLSMultiple()  local
1327       if (!STI->hasMinSize() || !BaseKill)  in MergeBaseUpdateLSMultiple()
1351     .addReg(Base, getKillRegState(BaseKill))  in MergeBaseUpdateLSMultiple()
1475   bool BaseKill = getLoadStoreBaseOp(*MI).isKill();  in MergeBaseUpdateLoadStore()  local
1532                    .addReg(Base, getKillRegState(isLd ? BaseKill : false))  in MergeBaseUpdateLoadStore()
1736                           bool BaseKill, bool BaseUndef, ARMCC::CondCodes Pred,  in InsertLDR_STR()  argument
1743       .addReg(BaseReg, getKillRegState(BaseKill)|getUndefRegState(BaseUndef));  in InsertLDR_STR()
1752       .addReg(BaseReg, getKillRegState(BaseKill)|getUndefRegState(BaseUndef));  in InsertLDR_STR()
1795   bool BaseKill = BaseOp.isKill();  in FixInvalidRegPairOp()  local
1811         .addReg(BaseReg, getKillRegState(BaseKill))  in FixInvalidRegPairOp()
1819         .addReg(BaseReg, getKillRegState(BaseKill))  in FixInvalidRegPairOp()
1845                     false, BaseReg, BaseKill, BaseUndef, Pred, PredReg, TII,  in FixInvalidRegPairOp()
1862                     OddUndef, BaseReg, BaseKill, BaseUndef, Pred, PredReg, TII,  in FixInvalidRegPairOp()