Lines Matching refs:VECTOR_REG_CAST
1752 MAKE_CASE(ARMISD::VECTOR_REG_CAST) in getTargetNodeName()
4235 return DAG.getNode(ARMISD::VECTOR_REG_CAST, SDLoc(Op), Op.getValueType(), in LowerINTRINSIC_WO_CHAIN()
7929 return DAG.getNode(ARMISD::VECTOR_REG_CAST, dl, VT, VDup); in LowerBUILD_VECTOR()
7973 return DAG.getNode(ARMISD::VECTOR_REG_CAST, dl, VT, VDup); in LowerBUILD_VECTOR()
8315 Src.ShuffleVec = DAG.getNode(ARMISD::VECTOR_REG_CAST, dl, ShuffleVT, Src.ShuffleVec); in ReconstructShuffle()
8367 return DAG.getNode(ARMISD::VECTOR_REG_CAST, dl, VT, Shuffle); in ReconstructShuffle()
8650 SDValue BC = DAG.getNode(ARMISD::VECTOR_REG_CAST, dl, MVT::v4i32, Shuffled); in LowerVECTOR_SHUFFLE_i1()
8941 SDValue Lo = DAG.getNode(ARMISD::VECTOR_REG_CAST, dl, FromVT, V1); in LowerVECTOR_SHUFFLE()
8942 SDValue Hi = DAG.getNode(ARMISD::VECTOR_REG_CAST, dl, FromVT, in LowerVECTOR_SHUFFLE()
9173 NewV = DAG.getNode(ARMISD::VECTOR_REG_CAST, dl, MVT::v4i32, NewV); in LowerCONCAT_VECTORS_i1()
10266 PassThru.getOpcode() == ARMISD::VECTOR_REG_CAST) && in LowerMLOAD()
13384 Inp0 = DAG.getNode(ARMISD::VECTOR_REG_CAST, DL, LegalVecVT, Inp0); in PerformVQDMULHCombine()
13385 Inp1 = DAG.getNode(ARMISD::VECTOR_REG_CAST, DL, LegalVecVT, Inp1); in PerformVQDMULHCombine()
13387 SDValue Trunc = DAG.getNode(ARMISD::VECTOR_REG_CAST, DL, ExtVecVT, VQDMULH); in PerformVQDMULHCombine()
14193 SDValue New0a = DAG.getNode(ARMISD::VECTOR_REG_CAST, dl, MVT::v4i32, Op0); in PerformMVEVMULLCombine()
14194 SDValue New1a = DAG.getNode(ARMISD::VECTOR_REG_CAST, dl, MVT::v4i32, Op1); in PerformMVEVMULLCombine()
14200 SDValue New0a = DAG.getNode(ARMISD::VECTOR_REG_CAST, dl, MVT::v4i32, Op0); in PerformMVEVMULLCombine()
14201 SDValue New1a = DAG.getNode(ARMISD::VECTOR_REG_CAST, dl, MVT::v4i32, Op1); in PerformMVEVMULLCombine()
15089 BV.getOpcode() == ARMISD::VECTOR_REG_CAST) && in PerformVMOVRRDCombine()
15429 if (Op->getOpcode() == ARMISD::VECTOR_REG_CAST) { in PerformVECTOR_REG_CASTCombine()
15433 return DAG.getNode(ARMISD::VECTOR_REG_CAST, dl, VT, Op->getOperand(0)); in PerformVECTOR_REG_CASTCombine()
15552 DCI.DAG.getNode(ARMISD::VECTOR_REG_CAST, dl, MVT::v2f64, Op0), in PerformExtractEltToVMOVRRD()
15689 DAG.getNode(ARMISD::VECTOR_REG_CAST, DL, VT, Trunc.getOperand(0)), in PerformShuffleVMOVNCombine()
15690 DAG.getNode(ARMISD::VECTOR_REG_CAST, DL, VT, Trunc.getOperand(1)), in PerformShuffleVMOVNCombine()
15695 DAG.getNode(ARMISD::VECTOR_REG_CAST, DL, VT, Trunc.getOperand(1)), in PerformShuffleVMOVNCombine()
15696 DAG.getNode(ARMISD::VECTOR_REG_CAST, DL, VT, Trunc.getOperand(0)), in PerformShuffleVMOVNCombine()
16704 Extract = DAG.getNode(ARMISD::VECTOR_REG_CAST, DL, MVT::v4i32, FPTrunc); in PerformSplittingToNarrowingStores()
17840 DAG.getNode(ARMISD::VECTOR_REG_CAST, DL, MVT::v8f16, Loads[i]); in PerformSplittingToWideningLoad()
18008 SDValue Bitcast = DAG.getNode(ARMISD::VECTOR_REG_CAST, DL, VT, VQMOVN); in PerformMinMaxCombine()
18049 SDValue Bitcast = DAG.getNode(ARMISD::VECTOR_REG_CAST, DL, VT, VQMOVN); in PerformMinMaxCombine()
18562 while (Src.getOpcode() == ARMISD::VECTOR_REG_CAST) in PerformBITCASTCombine()
18573 return DAG.getNode(ARMISD::VECTOR_REG_CAST, SDLoc(N), DstVT, Src); in PerformBITCASTCombine()
18619 DAG.getNode(ARMISD::VECTOR_REG_CAST, DL, VT, S0->getOperand(0)), in PerformMVETruncCombine()
18620 DAG.getNode(ARMISD::VECTOR_REG_CAST, DL, VT, S0->getOperand(1)), in PerformMVETruncCombine()
18625 DAG.getNode(ARMISD::VECTOR_REG_CAST, DL, VT, S0->getOperand(1)), in PerformMVETruncCombine()
18626 DAG.getNode(ARMISD::VECTOR_REG_CAST, DL, VT, S0->getOperand(0)), in PerformMVETruncCombine()
18764 SDValue VVT = DAG.getNode(ARMISD::VECTOR_REG_CAST, DL, VT, V); in PerformMVEExtCombine()
18941 case ARMISD::VECTOR_REG_CAST: in PerformDAGCombine()