Lines Matching refs:DCI
12575 TargetLowering::DAGCombinerInfo &DCI, in combineSelectAndUse() argument
12577 SelectionDAG &DAG = DCI.DAG; in combineSelectAndUse()
12601 TargetLowering::DAGCombinerInfo &DCI) { in combineSelectAndUseCommutative() argument
12605 if (SDValue Result = combineSelectAndUse(N, N0, N1, DCI, AllOnes)) in combineSelectAndUseCommutative()
12608 if (SDValue Result = combineSelectAndUse(N, N1, N0, DCI, AllOnes)) in combineSelectAndUseCommutative()
12626 TargetLowering::DAGCombinerInfo &DCI, in AddCombineToVPADD() argument
12638 SelectionDAG &DAG = DCI.DAG; in AddCombineToVPADD()
12654 TargetLowering::DAGCombinerInfo &DCI, in AddCombineVUZPToVPADDL() argument
12678 SelectionDAG &DAG = DCI.DAG; in AddCombineVUZPToVPADDL()
12707 TargetLowering::DAGCombinerInfo &DCI, in AddCombineBUILD_VECTORToVPADDL() argument
12711 if (DCI.isBeforeLegalize() || !Subtarget->hasNEON() in AddCombineBUILD_VECTORToVPADDL()
12772 SelectionDAG &DAG = DCI.DAG; in AddCombineBUILD_VECTORToVPADDL()
12811 TargetLowering::DAGCombinerInfo &DCI, in AddCombineTo64BitSMLAL16() argument
12846 SelectionDAG &DAG = DCI.DAG; in AddCombineTo64BitSMLAL16()
12888 TargetLowering::DAGCombinerInfo &DCI, in AddCombineTo64bitMLAL() argument
12944 return AddCombineTo64BitSMLAL16(AddcSubcNode, AddeSubeNode, DCI, Subtarget); in AddCombineTo64bitMLAL()
13004 SelectionDAG &DAG = DCI.DAG; in AddCombineTo64bitMLAL()
13054 TargetLowering::DAGCombinerInfo &DCI, in AddCombineTo64bitUMAAL() argument
13063 return AddCombineTo64bitMLAL(AddeNode, DCI, Subtarget); in AddCombineTo64bitUMAAL()
13080 return AddCombineTo64bitMLAL(AddeNode, DCI, Subtarget); in AddCombineTo64bitUMAAL()
13092 SelectionDAG &DAG = DCI.DAG; in AddCombineTo64bitUMAAL()
13131 TargetLowering::DAGCombinerInfo &DCI, in PerformAddcSubcCombine() argument
13133 SelectionDAG &DAG(DCI.DAG); in PerformAddcSubcCombine()
13142 return DCI.CombineTo(N, SDValue(N, 0), LHS->getOperand(2)); in PerformAddcSubcCombine()
13164 TargetLowering::DAGCombinerInfo &DCI, in PerformAddeSubeCombine() argument
13167 SelectionDAG &DAG = DCI.DAG; in PerformAddeSubeCombine()
13186 return AddCombineTo64bitMLAL(N, DCI, Subtarget); in PerformAddeSubeCombine()
13192 TargetLowering::DAGCombinerInfo &DCI, in PerformSELECTCombine() argument
13283 LHS = DCI.DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS); in PerformSELECTCombine()
13287 DCI.DAG.getNode(Opcode, dl, MVT::i32, LHS, RHS->getOperand(0)); in PerformSELECTCombine()
13291 Reduction = DCI.DAG.getNode(ISD::TRUNCATE, dl, VectorScalarType, Reduction); in PerformSELECTCombine()
13411 TargetLowering::DAGCombinerInfo &DCI, in PerformVSELECTCombine() argument
13416 if (SDValue V = PerformVQDMULHCombine(N, DCI.DAG)) in PerformVSELECTCombine()
13446 return DCI.DAG.getNode(ISD::VSELECT, SDLoc(N), Type, Cond, RHS, LHS); in PerformVSELECTCombine()
13451 TargetLowering::DAGCombinerInfo &DCI, in PerformVSetCCToVCTPCombine() argument
13459 !DCI.DAG.getTargetLoweringInfo().isTypeLegal(VT)) in PerformVSetCCToVCTPCombine()
13480 SDValue Op1S = DCI.DAG.getSplatValue(Op1); in PerformVSetCCToVCTPCombine()
13503 return DCI.DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, in PerformVSetCCToVCTPCombine()
13504 DCI.DAG.getConstant(Opc, DL, MVT::i32), in PerformVSetCCToVCTPCombine()
13505 DCI.DAG.getZExtOrTrunc(Op1S, DL, MVT::i32)); in PerformVSetCCToVCTPCombine()
13509 TargetLowering::DAGCombinerInfo &DCI, in PerformABSCombine() argument
13511 SelectionDAG &DAG = DCI.DAG; in PerformABSCombine()
13524 TargetLowering::DAGCombinerInfo &DCI, in PerformADDECombine() argument
13528 return PerformAddeSubeCombine(N, DCI, Subtarget); in PerformADDECombine()
13531 if (DCI.isBeforeLegalize()) return SDValue(); in PerformADDECombine()
13533 return AddCombineTo64bitUMAAL(N, DCI, Subtarget); in PerformADDECombine()
13541 TargetLowering::DAGCombinerInfo &DCI, in PerformADDCombineWithOperands() argument
13544 if (SDValue Result = AddCombineToVPADD(N, N0, N1, DCI, Subtarget)) in PerformADDCombineWithOperands()
13548 if (SDValue Result = AddCombineVUZPToVPADDL(N, N0, N1, DCI, Subtarget)) in PerformADDCombineWithOperands()
13550 if (SDValue Result = AddCombineBUILD_VECTORToVPADDL(N, N0, N1, DCI, in PerformADDCombineWithOperands()
13556 if (SDValue Result = combineSelectAndUse(N, N0, N1, DCI)) in PerformADDCombineWithOperands()
13910 TargetLowering::DAGCombinerInfo &DCI, in PerformSHLSimplify() argument
13913 if (DCI.isBeforeLegalize()) in PerformSHLSimplify()
14000 SelectionDAG &DAG = DCI.DAG; in PerformSHLSimplify()
14018 TargetLowering::DAGCombinerInfo &DCI, in PerformADDCombine() argument
14024 if (SDValue Result = PerformSHLSimplify(N, DCI, Subtarget)) in PerformADDCombine()
14027 if (SDValue Result = PerformADDVecReduce(N, DCI.DAG, Subtarget)) in PerformADDCombine()
14031 if (SDValue Result = PerformADDCombineWithOperands(N, N0, N1, DCI, Subtarget)) in PerformADDCombine()
14035 return PerformADDCombineWithOperands(N, N1, N0, DCI, Subtarget); in PerformADDCombine()
14061 TargetLowering::DAGCombinerInfo &DCI, in PerformSUBCombine() argument
14068 if (SDValue Result = combineSelectAndUse(N, N1, N0, DCI)) in PerformSUBCombine()
14071 if (SDValue R = PerformSubCSINCCombine(N, DCI.DAG)) in PerformSUBCombine()
14092 SDValue Negate = DCI.DAG.getNode(ISD::SUB, dl, MVT::i32, in PerformSUBCombine()
14093 DCI.DAG.getConstant(0, dl, MVT::i32), in PerformSUBCombine()
14095 return DCI.DAG.getNode(ARMISD::VDUP, dl, N->getValueType(0), Negate); in PerformSUBCombine()
14114 TargetLowering::DAGCombinerInfo &DCI, in PerformVMULCombine() argument
14119 SelectionDAG &DAG = DCI.DAG; in PerformVMULCombine()
14210 TargetLowering::DAGCombinerInfo &DCI, in PerformMULCombine() argument
14212 SelectionDAG &DAG = DCI.DAG; in PerformMULCombine()
14221 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer()) in PerformMULCombine()
14225 return PerformVMULCombine(N, DCI, Subtarget); in PerformMULCombine()
14291 DCI.CombineTo(N, Res, false); in PerformMULCombine()
14296 TargetLowering::DAGCombinerInfo &DCI, in CombineANDShift() argument
14299 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer()) in CombineANDShift()
14337 SelectionDAG &DAG = DCI.DAG; in CombineANDShift()
14400 TargetLowering::DAGCombinerInfo &DCI, in PerformANDCombine() argument
14406 SelectionDAG &DAG = DCI.DAG; in PerformANDCombine()
14434 if (SDValue Result = combineSelectAndUseCommutative(N, true, DCI)) in PerformANDCombine()
14437 if (SDValue Result = PerformSHLSimplify(N, DCI, Subtarget)) in PerformANDCombine()
14442 if (SDValue Result = CombineANDShift(N, DCI, Subtarget)) in PerformANDCombine()
14450 TargetLowering::DAGCombinerInfo &DCI, in PerformORCombineToSMULWBT() argument
14487 SelectionDAG &DAG = DCI.DAG; in PerformORCombineToSMULWBT()
14510 TargetLowering::DAGCombinerInfo &DCI, in PerformORCombineToBFI() argument
14519 SelectionDAG &DAG = DCI.DAG; in PerformORCombineToBFI()
14561 DCI.CombineTo(N, Res, false); in PerformORCombineToBFI()
14588 DCI.CombineTo(N, Res, false); in PerformORCombineToBFI()
14605 DCI.CombineTo(N, Res, false); in PerformORCombineToBFI()
14626 DCI.CombineTo(N, Res, false); in PerformORCombineToBFI()
14693 TargetLowering::DAGCombinerInfo &DCI, in PerformORCombine() argument
14699 SelectionDAG &DAG = DCI.DAG; in PerformORCombine()
14730 if (SDValue Result = combineSelectAndUseCommutative(N, false, DCI)) in PerformORCombine()
14732 if (SDValue Result = PerformORCombineToSMULWBT(N, DCI, Subtarget)) in PerformORCombine()
14782 if (SDValue Res = PerformORCombineToBFI(N, DCI, Subtarget)) in PerformORCombine()
14786 if (SDValue Result = PerformSHLSimplify(N, DCI, Subtarget)) in PerformORCombine()
14793 TargetLowering::DAGCombinerInfo &DCI, in PerformXORCombine() argument
14796 SelectionDAG &DAG = DCI.DAG; in PerformXORCombine()
14803 if (SDValue Result = combineSelectAndUseCommutative(N, false, DCI)) in PerformXORCombine()
14806 if (SDValue Result = PerformSHLSimplify(N, DCI, Subtarget)) in PerformXORCombine()
15041 TargetLowering::DAGCombinerInfo &DCI, in PerformVMOVRRDCombine() argument
15046 return DCI.CombineTo(N, InDouble.getOperand(0), InDouble.getOperand(1)); in PerformVMOVRRDCombine()
15057 SelectionDAG &DAG = DCI.DAG; in PerformVMOVRRDCombine()
15073 if (DCI.DAG.getDataLayout().isBigEndian()) in PerformVMOVRRDCombine()
15075 SDValue Result = DCI.CombineTo(N, NewLD1, NewLD2); in PerformVMOVRRDCombine()
15106 return DCI.DAG.getMergeValues({Op0, Op1}, SDLoc(N)); in PerformVMOVRRDCombine()
15124 return DCI.DAG.getMergeValues({Op0, Op1}, SDLoc(N)); in PerformVMOVRRDCombine()
15149 TargetLowering::DAGCombinerInfo &DCI) { in PerformVMOVhrCombine() argument
15173 DCI.DAG.getNode(ISD::CopyFromReg, SDLoc(N), in PerformVMOVhrCombine()
15174 DCI.DAG.getVTList(ArrayRef(OutTys, HasGlue ? 3 : 2)), in PerformVMOVhrCombine()
15178 DCI.DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), NewCopy.getValue(0)); in PerformVMOVhrCombine()
15179 DCI.DAG.ReplaceAllUsesOfValueWith(Copy.getValue(1), NewCopy.getValue(1)); in PerformVMOVhrCombine()
15181 DCI.DAG.ReplaceAllUsesOfValueWith(Copy.getValue(2), in PerformVMOVhrCombine()
15193 DCI.DAG.getLoad(N->getValueType(0), SDLoc(N), LN0->getChain(), in PerformVMOVhrCombine()
15195 DCI.DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Load.getValue(0)); in PerformVMOVhrCombine()
15196 DCI.DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), Load.getValue(1)); in PerformVMOVhrCombine()
15203 const TargetLowering &TLI = DCI.DAG.getTargetLoweringInfo(); in PerformVMOVhrCombine()
15204 if (TLI.SimplifyDemandedBits(Op0, DemandedMask, DCI)) in PerformVMOVhrCombine()
15258 TargetLowering::DAGCombinerInfo &DCI, in PerformBUILD_VECTORCombine() argument
15264 SelectionDAG &DAG = DCI.DAG; in PerformBUILD_VECTORCombine()
15281 DCI.AddToWorklist(V.getNode()); in PerformBUILD_VECTORCombine()
15290 PerformARMBUILD_VECTORCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI) { in PerformARMBUILD_VECTORCombine() argument
15343 SelectionDAG &DAG = DCI.DAG; in PerformARMBUILD_VECTORCombine()
15369 DCI.AddToWorklist(V.getNode()); in PerformARMBUILD_VECTORCombine()
15376 DCI.AddToWorklist(Vec.getNode()); in PerformARMBUILD_VECTORCombine()
15381 PerformPREDICATE_CASTCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI) { in PerformPREDICATE_CASTCombine() argument
15391 return DCI.DAG.getNode(ARMISD::PREDICATE_CAST, dl, VT, Op->getOperand(0)); in PerformPREDICATE_CASTCombine()
15398 DCI.DAG.getNode(ARMISD::PREDICATE_CAST, dl, VT, Op->getOperand(0)); in PerformPREDICATE_CASTCombine()
15399 SDValue C = DCI.DAG.getNode(ARMISD::PREDICATE_CAST, dl, VT, in PerformPREDICATE_CASTCombine()
15400 DCI.DAG.getConstant(65535, dl, MVT::i32)); in PerformPREDICATE_CASTCombine()
15401 return DCI.DAG.getNode(ISD::XOR, dl, VT, X, C); in PerformPREDICATE_CASTCombine()
15407 const TargetLowering &TLI = DCI.DAG.getTargetLoweringInfo(); in PerformPREDICATE_CASTCombine()
15408 if (TLI.SimplifyDemandedBits(Op, DemandedMask, DCI)) in PerformPREDICATE_CASTCombine()
15472 TargetLowering::DAGCombinerInfo &DCI) { in PerformInsertEltCombine() argument
15481 SelectionDAG &DAG = DCI.DAG; in PerformInsertEltCombine()
15488 DCI.AddToWorklist(Vec.getNode()); in PerformInsertEltCombine()
15489 DCI.AddToWorklist(V.getNode()); in PerformInsertEltCombine()
15500 PerformExtractEltToVMOVRRD(SDNode *N, TargetLowering::DAGCombinerInfo &DCI) { in PerformExtractEltToVMOVRRD() argument
15504 if (!DCI.isAfterLegalizeDAG() || VT != MVT::i32 || in PerformExtractEltToVMOVRRD()
15505 !DCI.DAG.getTargetLoweringInfo().isTypeLegal(MVT::f64)) in PerformExtractEltToVMOVRRD()
15550 SDValue F64 = DCI.DAG.getNode( in PerformExtractEltToVMOVRRD()
15552 DCI.DAG.getNode(ARMISD::VECTOR_REG_CAST, dl, MVT::v2f64, Op0), in PerformExtractEltToVMOVRRD()
15553 DCI.DAG.getConstant(Ext.getConstantOperandVal(1) / 2, dl, MVT::i32)); in PerformExtractEltToVMOVRRD()
15555 DCI.DAG.getNode(ARMISD::VMOVRRD, dl, {MVT::i32, MVT::i32}, F64); in PerformExtractEltToVMOVRRD()
15557 DCI.CombineTo(OtherExt.getNode(), SDValue(VMOVRRD.getNode(), 1)); in PerformExtractEltToVMOVRRD()
15562 TargetLowering::DAGCombinerInfo &DCI, in PerformExtractEltCombine() argument
15572 return DCI.DAG.getNode(ARMISD::VMOVhr, dl, VT, X); in PerformExtractEltCombine()
15574 return DCI.DAG.getNode(ARMISD::VMOVrh, dl, VT, X); in PerformExtractEltCombine()
15576 return DCI.DAG.getNode(ISD::BITCAST, dl, VT, X); in PerformExtractEltCombine()
15605 if (SDValue R = PerformExtractEltToVMOVRRD(N, DCI)) in PerformExtractEltCombine()
15615 return DCI.DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Op0.getOperand(Vec), in PerformExtractEltCombine()
15616 DCI.DAG.getConstant(SubIdx, dl, MVT::i32)); in PerformExtractEltCombine()
15637 PerformInsertSubvectorCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI) { in PerformInsertSubvectorCombine() argument
15646 !DCI.DAG.getTargetLoweringInfo().isTypeLegal(VecVT) || in PerformInsertSubvectorCombine()
15647 !DCI.DAG.getTargetLoweringInfo().isTypeLegal(SubVT)) in PerformInsertSubvectorCombine()
15667 Hi = DCI.DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT, Vec, in PerformInsertSubvectorCombine()
15668 DCI.DAG.getVectorIdxConstant(NumSubElts, DL)); in PerformInsertSubvectorCombine()
15670 Lo = DCI.DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT, Vec, in PerformInsertSubvectorCombine()
15671 DCI.DAG.getVectorIdxConstant(0, DL)); in PerformInsertSubvectorCombine()
15674 return DCI.DAG.getNode(ISD::CONCAT_VECTORS, DL, VecVT, Lo, Hi); in PerformInsertSubvectorCombine()
15777 TargetLowering::DAGCombinerInfo &DCI) { in TryCombineBaseUpdate() argument
15778 SelectionDAG &DAG = DCI.DAG; in TryCombineBaseUpdate()
16069 DCI.CombineTo(N, NewResults); in TryCombineBaseUpdate()
16070 DCI.CombineTo(User.N, SDValue(UpdN.getNode(), NumResultVecs)); in TryCombineBaseUpdate()
16144 TargetLowering::DAGCombinerInfo &DCI) { in CombineBaseUpdate() argument
16165 getPointerConstIncrement(User->getOpcode(), Addr, Inc, DCI.DAG); in CombineBaseUpdate()
16177 getPointerConstIncrement(Addr->getOpcode(), Base, CInc, DCI.DAG); in CombineBaseUpdate()
16188 getPointerConstIncrement(User->getOpcode(), Base, UserInc, DCI.DAG); in CombineBaseUpdate()
16194 SDValue NewInc = DCI.DAG.getConstant(NewConstInc, SDLoc(N), MVT::i32); in CombineBaseUpdate()
16212 if (TryCombineBaseUpdate(Target, User, /*SimpleConstIncOnly=*/true, DCI)) in CombineBaseUpdate()
16226 if (TryCombineBaseUpdate(Target, User, /*SimpleConstIncOnly=*/false, DCI)) in CombineBaseUpdate()
16233 TargetLowering::DAGCombinerInfo &DCI) { in PerformVLDCombine() argument
16234 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer()) in PerformVLDCombine()
16237 return CombineBaseUpdate(N, DCI); in PerformVLDCombine()
16241 TargetLowering::DAGCombinerInfo &DCI) { in PerformMVEVLDCombine() argument
16242 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer()) in PerformMVEVLDCombine()
16245 SelectionDAG &DAG = DCI.DAG; in PerformMVEVLDCombine()
16351 DCI.CombineTo(N, NewResults); in PerformMVEVLDCombine()
16352 DCI.CombineTo(User, SDValue(UpdN.getNode(), NumResultVecs)); in PerformMVEVLDCombine()
16364 static bool CombineVLDDUP(SDNode *N, TargetLowering::DAGCombinerInfo &DCI) { in CombineVLDDUP() argument
16365 SelectionDAG &DAG = DCI.DAG; in CombineVLDDUP()
16426 DCI.CombineTo(User, SDValue(VLDDup.getNode(), ResNo)); in CombineVLDDUP()
16435 DCI.CombineTo(VLD, VLDDupResults); in CombineVLDDUP()
16443 TargetLowering::DAGCombinerInfo &DCI, in PerformVDUPLANECombine() argument
16452 if (!DCI.DAG.getTargetLoweringInfo().isTypeLegal(ExtractVT)) in PerformVDUPLANECombine()
16454 SDValue Extract = DCI.DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(N), ExtractVT, in PerformVDUPLANECombine()
16456 return DCI.DAG.getNode(ARMISD::VDUP, SDLoc(N), VT, Extract); in PerformVDUPLANECombine()
16461 if (CombineVLDDUP(N, DCI)) in PerformVDUPLANECombine()
16481 return DCI.DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Op); in PerformVDUPLANECombine()
16524 TargetLowering::DAGCombinerInfo &DCI, in PerformLOADCombine() argument
16530 DCI.DAG.getTargetLoweringInfo().isTypeLegal(VT)) in PerformLOADCombine()
16531 return CombineBaseUpdate(N, DCI); in PerformLOADCombine()
16794 TargetLowering::DAGCombinerInfo &DCI, in PerformSTORECombine() argument
16803 if (SDValue Store = PerformTruncatingStoreCombine(St, DCI.DAG)) in PerformSTORECombine()
16807 if (SDValue NewToken = PerformSplittingToNarrowingStores(St, DCI.DAG)) in PerformSTORECombine()
16809 if (SDValue NewChain = PerformExtractFpToIntStores(St, DCI.DAG)) in PerformSTORECombine()
16812 PerformSplittingMVETruncToNarrowingStores(St, DCI.DAG)) in PerformSTORECombine()
16823 SelectionDAG &DAG = DCI.DAG; in PerformSTORECombine()
16846 SelectionDAG &DAG = DCI.DAG; in PerformSTORECombine()
16857 DCI.AddToWorklist(Vec.getNode()); in PerformSTORECombine()
16858 DCI.AddToWorklist(ExtElt.getNode()); in PerformSTORECombine()
16859 DCI.AddToWorklist(V.getNode()); in PerformSTORECombine()
16867 DCI.DAG.getTargetLoweringInfo().isTypeLegal(VT)) in PerformSTORECombine()
16868 return CombineBaseUpdate(N, DCI); in PerformSTORECombine()
17366 TargetLowering::DAGCombinerInfo &DCI) { in PerformVMOVNCombine() argument
17384 return DCI.DAG.getNode(Op1->getOpcode(), SDLoc(Op1), N->getValueType(0), in PerformVMOVNCombine()
17396 const TargetLowering &TLI = DCI.DAG.getTargetLoweringInfo(); in PerformVMOVNCombine()
17397 if (TLI.SimplifyDemandedVectorElts(Op0, Op0DemandedElts, DCI)) in PerformVMOVNCombine()
17399 if (TLI.SimplifyDemandedVectorElts(Op1, Op1DemandedElts, DCI)) in PerformVMOVNCombine()
17406 TargetLowering::DAGCombinerInfo &DCI) { in PerformVQMOVNCombine() argument
17415 const TargetLowering &TLI = DCI.DAG.getTargetLoweringInfo(); in PerformVQMOVNCombine()
17416 if (TLI.SimplifyDemandedVectorElts(Op0, Op0DemandedElts, DCI)) in PerformVQMOVNCombine()
17422 TargetLowering::DAGCombinerInfo &DCI) { in PerformVQDMULHCombine() argument
17434 SDValue NewBinOp = DCI.DAG.getNode(N->getOpcode(), DL, VT, in PerformVQDMULHCombine()
17437 return DCI.DAG.getVectorShuffle(VT, DL, NewBinOp, UndefV, Shuf0->getMask()); in PerformVQDMULHCombine()
17472 DAGCombinerInfo &DCI) const { in PerformIntrinsicCombine()
17473 SelectionDAG &DAG = DCI.DAG; in PerformIntrinsicCombine()
17639 if (SimplifyDemandedBits(N->getOperand(3), DemandedMask, DCI)) in PerformIntrinsicCombine()
17656 if (SimplifyDemandedBits(N->getOperand(1), DemandedMask, DCI)) in PerformIntrinsicCombine()
17699 TargetLowering::DAGCombinerInfo &DCI, in PerformShiftCombine() argument
17701 SelectionDAG &DAG = DCI.DAG; in PerformShiftCombine()
17707 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer()) in PerformShiftCombine()
18198 TargetLowering::DAGCombinerInfo &DCI, in PerformHWLoopCombine() argument
18263 SelectionDAG &DAG = DCI.DAG; in PerformHWLoopCombine()
18547 TargetLowering::DAGCombinerInfo &DCI, in PerformBITCASTCombine() argument
18549 SelectionDAG &DAG = DCI.DAG; in PerformBITCASTCombine()
18576 if (SDValue R = PerformExtractEltToVMOVRRD(N, DCI)) in PerformBITCASTCombine()
18585 SDNode *N, TargetLowering::DAGCombinerInfo &DCI) const { in PerformMVETruncCombine()
18586 SelectionDAG &DAG = DCI.DAG; in PerformMVETruncCombine()
18655 if (!DCI.isAfterLegalizeDAG()) in PerformMVETruncCombine()
18754 SDNode *N, TargetLowering::DAGCombinerInfo &DCI) const { in PerformMVEExtCombine()
18755 SelectionDAG &DAG = DCI.DAG; in PerformMVEExtCombine()
18821 if (!DCI.isAfterLegalizeDAG()) in PerformMVEExtCombine()
18858 DAGCombinerInfo &DCI) const { in PerformDAGCombine()
18862 case ISD::SELECT: return PerformSELECTCombine(N, DCI, Subtarget); in PerformDAGCombine()
18863 case ISD::VSELECT: return PerformVSELECTCombine(N, DCI, Subtarget); in PerformDAGCombine()
18864 case ISD::SETCC: return PerformVSetCCToVCTPCombine(N, DCI, Subtarget); in PerformDAGCombine()
18865 case ISD::ABS: return PerformABSCombine(N, DCI, Subtarget); in PerformDAGCombine()
18866 case ARMISD::ADDE: return PerformADDECombine(N, DCI, Subtarget); in PerformDAGCombine()
18867 case ARMISD::UMLAL: return PerformUMLALCombine(N, DCI.DAG, Subtarget); in PerformDAGCombine()
18868 case ISD::ADD: return PerformADDCombine(N, DCI, Subtarget); in PerformDAGCombine()
18869 case ISD::SUB: return PerformSUBCombine(N, DCI, Subtarget); in PerformDAGCombine()
18870 case ISD::MUL: return PerformMULCombine(N, DCI, Subtarget); in PerformDAGCombine()
18871 case ISD::OR: return PerformORCombine(N, DCI, Subtarget); in PerformDAGCombine()
18872 case ISD::XOR: return PerformXORCombine(N, DCI, Subtarget); in PerformDAGCombine()
18873 case ISD::AND: return PerformANDCombine(N, DCI, Subtarget); in PerformDAGCombine()
18875 case ISD::BR_CC: return PerformHWLoopCombine(N, DCI, Subtarget); in PerformDAGCombine()
18877 case ARMISD::SUBC: return PerformAddcSubcCombine(N, DCI, Subtarget); in PerformDAGCombine()
18878 case ARMISD::SUBE: return PerformAddeSubeCombine(N, DCI, Subtarget); in PerformDAGCombine()
18879 case ARMISD::BFI: return PerformBFICombine(N, DCI.DAG); in PerformDAGCombine()
18880 case ARMISD::VMOVRRD: return PerformVMOVRRDCombine(N, DCI, Subtarget); in PerformDAGCombine()
18881 case ARMISD::VMOVDRR: return PerformVMOVDRRCombine(N, DCI.DAG); in PerformDAGCombine()
18882 case ARMISD::VMOVhr: return PerformVMOVhrCombine(N, DCI); in PerformDAGCombine()
18883 case ARMISD::VMOVrh: return PerformVMOVrhCombine(N, DCI.DAG); in PerformDAGCombine()
18884 case ISD::STORE: return PerformSTORECombine(N, DCI, Subtarget); in PerformDAGCombine()
18885 case ISD::BUILD_VECTOR: return PerformBUILD_VECTORCombine(N, DCI, Subtarget); in PerformDAGCombine()
18886 case ISD::INSERT_VECTOR_ELT: return PerformInsertEltCombine(N, DCI); in PerformDAGCombine()
18888 return PerformExtractEltCombine(N, DCI, Subtarget); in PerformDAGCombine()
18889 case ISD::SIGN_EXTEND_INREG: return PerformSignExtendInregCombine(N, DCI.DAG); in PerformDAGCombine()
18890 case ISD::INSERT_SUBVECTOR: return PerformInsertSubvectorCombine(N, DCI); in PerformDAGCombine()
18891 case ISD::VECTOR_SHUFFLE: return PerformVECTOR_SHUFFLECombine(N, DCI.DAG); in PerformDAGCombine()
18892 case ARMISD::VDUPLANE: return PerformVDUPLANECombine(N, DCI, Subtarget); in PerformDAGCombine()
18893 case ARMISD::VDUP: return PerformVDUPCombine(N, DCI.DAG, Subtarget); in PerformDAGCombine()
18896 return PerformVCVTCombine(N, DCI.DAG, Subtarget); in PerformDAGCombine()
18898 return PerformFADDCombine(N, DCI.DAG, Subtarget); in PerformDAGCombine()
18900 return PerformVDIVCombine(N, DCI.DAG, Subtarget); in PerformDAGCombine()
18902 return PerformIntrinsicCombine(N, DCI); in PerformDAGCombine()
18906 return PerformShiftCombine(N, DCI, Subtarget); in PerformDAGCombine()
18910 return PerformExtendCombine(N, DCI.DAG, Subtarget); in PerformDAGCombine()
18912 return PerformFPExtendCombine(N, DCI.DAG, Subtarget); in PerformDAGCombine()
18917 return PerformMinMaxCombine(N, DCI.DAG, Subtarget); in PerformDAGCombine()
18919 return PerformCMOVCombine(N, DCI.DAG); in PerformDAGCombine()
18921 return PerformBRCONDCombine(N, DCI.DAG); in PerformDAGCombine()
18923 return PerformCMPZCombine(N, DCI.DAG); in PerformDAGCombine()
18927 return PerformCSETCombine(N, DCI.DAG); in PerformDAGCombine()
18929 return PerformLOADCombine(N, DCI, Subtarget); in PerformDAGCombine()
18934 return PerformVLDCombine(N, DCI); in PerformDAGCombine()
18936 return PerformARMBUILD_VECTORCombine(N, DCI); in PerformDAGCombine()
18938 return PerformBITCASTCombine(N, DCI, Subtarget); in PerformDAGCombine()
18940 return PerformPREDICATE_CASTCombine(N, DCI); in PerformDAGCombine()
18942 return PerformVECTOR_REG_CASTCombine(N, DCI.DAG, Subtarget); in PerformDAGCombine()
18944 return PerformMVETruncCombine(N, DCI); in PerformDAGCombine()
18947 return PerformMVEExtCombine(N, DCI); in PerformDAGCombine()
18949 return PerformVCMPCombine(N, DCI.DAG, Subtarget); in PerformDAGCombine()
18951 return PerformVECREDUCE_ADDCombine(N, DCI.DAG, Subtarget); in PerformDAGCombine()
18964 return PerformReduceShuffleCombine(N, DCI.DAG); in PerformDAGCombine()
18966 return PerformVMOVNCombine(N, DCI); in PerformDAGCombine()
18969 return PerformVQMOVNCombine(N, DCI); in PerformDAGCombine()
18971 return PerformVQDMULHCombine(N, DCI); in PerformDAGCombine()
18975 return PerformLongShiftCombine(N, DCI.DAG); in PerformDAGCombine()
18979 if (SimplifyDemandedBits(N->getOperand(1), DemandedMask, DCI)) in PerformDAGCombine()
18986 if (SimplifyDemandedBits(N->getOperand(1), DemandedMask, DCI)) in PerformDAGCombine()
18997 if ((SimplifyDemandedBits(N->getOperand(0), DemandedMask, DCI)) || in PerformDAGCombine()
18998 (SimplifyDemandedBits(N->getOperand(1), DemandedMask, DCI))) in PerformDAGCombine()
19007 if ((SimplifyDemandedBits(N->getOperand(0), LowMask, DCI)) || in PerformDAGCombine()
19008 (SimplifyDemandedBits(N->getOperand(1), HighMask, DCI))) in PerformDAGCombine()
19017 if ((SimplifyDemandedBits(N->getOperand(0), HighMask, DCI)) || in PerformDAGCombine()
19018 (SimplifyDemandedBits(N->getOperand(1), LowMask, DCI))) in PerformDAGCombine()
19025 if ((SimplifyDemandedBits(N->getOperand(0), DemandedMask, DCI)) || in PerformDAGCombine()
19026 (SimplifyDemandedBits(N->getOperand(1), DemandedMask, DCI))) in PerformDAGCombine()
19036 if ((SimplifyDemandedBits(N->getOperand(0), DemandedMask, DCI)) || in PerformDAGCombine()
19037 (SimplifyDemandedBits(N->getOperand(1), DemandedMask, DCI))) in PerformDAGCombine()
19067 return PerformVLDCombine(N, DCI); in PerformDAGCombine()
19072 return PerformMVEVLDCombine(N, DCI); in PerformDAGCombine()