Lines Matching refs:Cnt
6593 static bool getVShiftImm(SDValue Op, unsigned ElementBits, int64_t &Cnt) { in getVShiftImm() argument
6606 Cnt = SplatBits.getSExtValue(); in getVShiftImm()
6614 static bool isVShiftLImm(SDValue Op, EVT VT, bool isLong, int64_t &Cnt) { in isVShiftLImm() argument
6617 if (!getVShiftImm(Op, ElementBits, Cnt)) in isVShiftLImm()
6619 return (Cnt >= 0 && (isLong ? Cnt - 1 : Cnt) < ElementBits); in isVShiftLImm()
6629 int64_t &Cnt) { in isVShiftRImm() argument
6632 if (!getVShiftImm(Op, ElementBits, Cnt)) in isVShiftRImm()
6635 return (Cnt >= 1 && Cnt <= (isNarrow ? ElementBits / 2 : ElementBits)); in isVShiftRImm()
6636 if (Cnt >= -(isNarrow ? ElementBits / 2 : ElementBits) && Cnt <= -1) { in isVShiftRImm()
6637 Cnt = -Cnt; in isVShiftRImm()
6647 int64_t Cnt; in LowerShift() local
6659 if (isVShiftLImm(N->getOperand(1), VT, false, Cnt)) in LowerShift()
6661 DAG.getConstant(Cnt, dl, MVT::i32)); in LowerShift()
6669 if (isVShiftRImm(N->getOperand(1), VT, false, false, Cnt)) { in LowerShift()
6673 DAG.getConstant(Cnt, dl, MVT::i32)); in LowerShift()
17500 int64_t Cnt; in PerformIntrinsicCombine() local
17506 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt)) { in PerformIntrinsicCombine()
17510 if (isVShiftRImm(N->getOperand(2), VT, false, true, Cnt)) { in PerformIntrinsicCombine()
17519 if (isVShiftRImm(N->getOperand(2), VT, false, true, Cnt)) in PerformIntrinsicCombine()
17525 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt)) in PerformIntrinsicCombine()
17530 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt)) in PerformIntrinsicCombine()
17542 if (isVShiftRImm(N->getOperand(2), VT, true, true, Cnt)) in PerformIntrinsicCombine()
17596 N->getOperand(1), DAG.getConstant(Cnt, dl, MVT::i32)); in PerformIntrinsicCombine()
17601 int64_t Cnt; in PerformIntrinsicCombine() local
17604 if (isVShiftLImm(N->getOperand(3), VT, false, Cnt)) in PerformIntrinsicCombine()
17606 else if (isVShiftRImm(N->getOperand(3), VT, false, true, Cnt)) in PerformIntrinsicCombine()
17615 DAG.getConstant(Cnt, dl, MVT::i32)); in PerformIntrinsicCombine()
17745 int64_t Cnt; in PerformShiftCombine() local
17751 if (isVShiftLImm(N->getOperand(1), VT, false, Cnt)) { in PerformShiftCombine()
17754 DAG.getConstant(Cnt, dl, MVT::i32)); in PerformShiftCombine()
17760 if (isVShiftRImm(N->getOperand(1), VT, false, false, Cnt)) { in PerformShiftCombine()
17765 DAG.getConstant(Cnt, dl, MVT::i32)); in PerformShiftCombine()