339   SDNode *createGPRPairNode(EVT VT, SDValue V0, SDValue V1);
340   SDNode *createSRegPairNode(EVT VT, SDValue V0, SDValue V1);
341   SDNode *createDRegPairNode(EVT VT, SDValue V0, SDValue V1);
342   SDNode *createQRegPairNode(EVT VT, SDValue V0, SDValue V1);
345   SDNode *createQuadSRegsNode(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
346   SDNode *createQuadDRegsNode(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
347   SDNode *createQuadQRegsNode(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
1847 SDNode *ARMDAGToDAGISel::createGPRPairNode(EVT VT, SDValue V0, SDValue V1) {  in createGPRPairNode()  argument
1848   SDLoc dl(V0.getNode());  in createGPRPairNode()
1853   const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 };  in createGPRPairNode()
1858 SDNode *ARMDAGToDAGISel::createSRegPairNode(EVT VT, SDValue V0, SDValue V1) {  in createSRegPairNode()  argument
1859   SDLoc dl(V0.getNode());  in createSRegPairNode()
1864   const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 };  in createSRegPairNode()
1869 SDNode *ARMDAGToDAGISel::createDRegPairNode(EVT VT, SDValue V0, SDValue V1) {  in createDRegPairNode()  argument
1870   SDLoc dl(V0.getNode());  in createDRegPairNode()
1875   const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 };  in createDRegPairNode()
1880 SDNode *ARMDAGToDAGISel::createQRegPairNode(EVT VT, SDValue V0, SDValue V1) {  in createQRegPairNode()  argument
1881   SDLoc dl(V0.getNode());  in createQRegPairNode()
1886   const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 };  in createQRegPairNode()
1891 SDNode *ARMDAGToDAGISel::createQuadSRegsNode(EVT VT, SDValue V0, SDValue V1,  in createQuadSRegsNode()  argument
1893   SDLoc dl(V0.getNode());  in createQuadSRegsNode()
1900   const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1,  in createQuadSRegsNode()
1906 SDNode *ARMDAGToDAGISel::createQuadDRegsNode(EVT VT, SDValue V0, SDValue V1,  in createQuadDRegsNode()  argument
1908   SDLoc dl(V0.getNode());  in createQuadDRegsNode()
1915   const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1,  in createQuadDRegsNode()
1921 SDNode *ARMDAGToDAGISel::createQuadQRegsNode(EVT VT, SDValue V0, SDValue V1,  in createQuadQRegsNode()  argument
1923   SDLoc dl(V0.getNode());  in createQuadQRegsNode()
1930   const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1,  in createQuadQRegsNode()
2312       SDValue V0 = N->getOperand(Vec0Idx + 0);  in SelectVST()  local
2315         SrcReg = SDValue(createDRegPairNode(MVT::v2i64, V0, V1), 0);  in SelectVST()
2323         SrcReg = SDValue(createQuadDRegsNode(MVT::v4i64, V0, V1, V2, V3), 0);  in SelectVST()
2368   SDValue V0 = N->getOperand(Vec0Idx + 0);  in SelectVST()  local
2374   SDValue RegSeq = SDValue(createQuadQRegsNode(MVT::v8i64, V0, V1, V2, V3), 0);  in SelectVST()
2487   SDValue V0 = N->getOperand(Vec0Idx + 0);  in SelectVLDSTLane()  local
2491       SuperReg = SDValue(createDRegPairNode(MVT::v2i64, V0, V1), 0);  in SelectVLDSTLane()
2493       SuperReg = SDValue(createQRegPairNode(MVT::v4i64, V0, V1), 0);  in SelectVLDSTLane()
2500       SuperReg = SDValue(createQuadDRegsNode(MVT::v4i64, V0, V1, V2, V3), 0);  in SelectVLDSTLane()
2502       SuperReg = SDValue(createQuadQRegsNode(MVT::v8i64, V0, V1, V2, V3), 0);  in SelectVLDSTLane()
5779     SDValue V0 = N->getOperand(i+1);  in tryInlineAsm()  local
5781     Register Reg0 = cast<RegisterSDNode>(V0)->getReg();  in tryInlineAsm()