Lines Matching refs:Ops
238 void AddMVEPredicateToOps(SDValueVector &Ops, SDLoc Loc,
241 void AddMVEPredicateToOps(SDValueVector &Ops, SDLoc Loc,
245 void AddEmptyMVEPredicateToOps(SDValueVector &Ops, SDLoc Loc);
247 void AddEmptyMVEPredicateToOps(SDValueVector &Ops, SDLoc Loc, EVT InactiveTy);
1645 SDValue Ops[]= { Base, AMOpc, getAL(CurDAG, SDLoc(N)), in tryARMIndexedLoad() local
1648 MVT::Other, Ops); in tryARMIndexedLoad()
1655 SDValue Ops[]= { Base, Offset, AMOpc, getAL(CurDAG, SDLoc(N)), in tryARMIndexedLoad() local
1658 MVT::Other, Ops); in tryARMIndexedLoad()
1686 SDValue Ops[]= { Base, getAL(CurDAG, SDLoc(N)), in tryT1IndexedLoad() local
1689 MVT::i32, MVT::Other, Ops); in tryT1IndexedLoad()
1734 SDValue Ops[]= { Base, Offset, getAL(CurDAG, SDLoc(N)), in tryT2IndexedLoad() local
1737 MVT::Other, Ops); in tryT2IndexedLoad()
1830 SDValue Ops[] = {Base, in tryMVEIndexedLoad() local
1837 N->getValueType(0), MVT::Other, Ops); in tryMVEIndexedLoad()
1853 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 }; in createGPRPairNode() local
1854 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops); in createGPRPairNode()
1864 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 }; in createSRegPairNode() local
1865 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops); in createSRegPairNode()
1875 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 }; in createDRegPairNode() local
1876 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops); in createDRegPairNode()
1886 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 }; in createQRegPairNode() local
1887 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops); in createQRegPairNode()
1900 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1, in createQuadSRegsNode() local
1902 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops); in createQuadSRegsNode()
1915 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1, in createQuadDRegsNode() local
1917 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops); in createQuadDRegsNode()
1930 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1, in createQuadQRegsNode() local
1932 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops); in createQuadQRegsNode()
2169 SmallVector<SDValue, 7> Ops; in SelectVLD() local
2175 Ops.push_back(MemAddr); in SelectVLD()
2176 Ops.push_back(Align); in SelectVLD()
2185 Ops.push_back(Inc); in SelectVLD()
2189 Ops.push_back(Reg0); in SelectVLD()
2191 Ops.push_back(Pred); in SelectVLD()
2192 Ops.push_back(Reg0); in SelectVLD()
2193 Ops.push_back(Chain); in SelectVLD()
2194 VLd = CurDAG->getMachineNode(Opc, dl, ResTys, Ops); in SelectVLD()
2211 Ops.push_back(SDValue(VLdA, 1)); in SelectVLD()
2212 Ops.push_back(Align); in SelectVLD()
2218 Ops.push_back(Reg0); in SelectVLD()
2220 Ops.push_back(SDValue(VLdA, 0)); in SelectVLD()
2221 Ops.push_back(Pred); in SelectVLD()
2222 Ops.push_back(Reg0); in SelectVLD()
2223 Ops.push_back(Chain); in SelectVLD()
2224 VLd = CurDAG->getMachineNode(QOpcodes1[OpcodeIndex], dl, ResTys, Ops); in SelectVLD()
2303 SmallVector<SDValue, 7> Ops; in SelectVST() local
2334 Ops.push_back(MemAddr); in SelectVST()
2335 Ops.push_back(Align); in SelectVST()
2344 Ops.push_back(Inc); in SelectVST()
2349 Ops.push_back(Reg0); in SelectVST()
2351 Ops.push_back(SrcReg); in SelectVST()
2352 Ops.push_back(Pred); in SelectVST()
2353 Ops.push_back(Reg0); in SelectVST()
2354 Ops.push_back(Chain); in SelectVST()
2355 SDNode *VSt = CurDAG->getMachineNode(Opc, dl, ResTys, Ops); in SelectVST()
2386 Ops.push_back(SDValue(VStA, 0)); in SelectVST()
2387 Ops.push_back(Align); in SelectVST()
2393 Ops.push_back(Reg0); in SelectVST()
2395 Ops.push_back(RegSeq); in SelectVST()
2396 Ops.push_back(Pred); in SelectVST()
2397 Ops.push_back(Reg0); in SelectVST()
2398 Ops.push_back(Chain); in SelectVST()
2400 Ops); in SelectVST()
2476 SmallVector<SDValue, 8> Ops; in SelectVLDSTLane() local
2477 Ops.push_back(MemAddr); in SelectVLDSTLane()
2478 Ops.push_back(Align); in SelectVLDSTLane()
2483 Ops.push_back(IsImmUpdate ? Reg0 : Inc); in SelectVLDSTLane()
2504 Ops.push_back(SuperReg); in SelectVLDSTLane()
2505 Ops.push_back(getI32Imm(Lane, dl)); in SelectVLDSTLane()
2506 Ops.push_back(Pred); in SelectVLDSTLane()
2507 Ops.push_back(Reg0); in SelectVLDSTLane()
2508 Ops.push_back(Chain); in SelectVLDSTLane()
2512 SDNode *VLdLn = CurDAG->getMachineNode(Opc, dl, ResTys, Ops); in SelectVLDSTLane()
2535 void ARMDAGToDAGISel::AddMVEPredicateToOps(SDValueVector &Ops, SDLoc Loc, in AddMVEPredicateToOps() argument
2537 Ops.push_back(CurDAG->getTargetConstant(ARMVCC::Then, Loc, MVT::i32)); in AddMVEPredicateToOps()
2538 Ops.push_back(PredicateMask); in AddMVEPredicateToOps()
2539 Ops.push_back(CurDAG->getRegister(0, MVT::i32)); // tp_reg in AddMVEPredicateToOps()
2543 void ARMDAGToDAGISel::AddMVEPredicateToOps(SDValueVector &Ops, SDLoc Loc, in AddMVEPredicateToOps() argument
2546 Ops.push_back(CurDAG->getTargetConstant(ARMVCC::Then, Loc, MVT::i32)); in AddMVEPredicateToOps()
2547 Ops.push_back(PredicateMask); in AddMVEPredicateToOps()
2548 Ops.push_back(CurDAG->getRegister(0, MVT::i32)); // tp_reg in AddMVEPredicateToOps()
2549 Ops.push_back(Inactive); in AddMVEPredicateToOps()
2553 void ARMDAGToDAGISel::AddEmptyMVEPredicateToOps(SDValueVector &Ops, SDLoc Loc) { in AddEmptyMVEPredicateToOps() argument
2554 Ops.push_back(CurDAG->getTargetConstant(ARMVCC::None, Loc, MVT::i32)); in AddEmptyMVEPredicateToOps()
2555 Ops.push_back(CurDAG->getRegister(0, MVT::i32)); in AddEmptyMVEPredicateToOps()
2556 Ops.push_back(CurDAG->getRegister(0, MVT::i32)); // tp_reg in AddEmptyMVEPredicateToOps()
2560 void ARMDAGToDAGISel::AddEmptyMVEPredicateToOps(SDValueVector &Ops, SDLoc Loc, in AddEmptyMVEPredicateToOps() argument
2562 Ops.push_back(CurDAG->getTargetConstant(ARMVCC::None, Loc, MVT::i32)); in AddEmptyMVEPredicateToOps()
2563 Ops.push_back(CurDAG->getRegister(0, MVT::i32)); in AddEmptyMVEPredicateToOps()
2564 Ops.push_back(CurDAG->getRegister(0, MVT::i32)); // tp_reg in AddEmptyMVEPredicateToOps()
2565 Ops.push_back(SDValue( in AddEmptyMVEPredicateToOps()
2572 SmallVector<SDValue, 8> Ops; in SelectMVE_WB() local
2586 Ops.push_back(N->getOperand(2)); // vector of base addresses in SelectMVE_WB()
2589 Ops.push_back(getI32Imm(ImmValue, Loc)); // immediate offset in SelectMVE_WB()
2592 AddMVEPredicateToOps(Ops, Loc, N->getOperand(4)); in SelectMVE_WB()
2594 AddEmptyMVEPredicateToOps(Ops, Loc); in SelectMVE_WB()
2596 Ops.push_back(N->getOperand(0)); // chain in SelectMVE_WB()
2603 SDNode *New = CurDAG->getMachineNode(Opcode, SDLoc(N), VTs, Ops); in SelectMVE_WB()
2615 SmallVector<SDValue, 8> Ops; in SelectMVE_LongShift() local
2618 Ops.push_back(N->getOperand(1)); in SelectMVE_LongShift()
2619 Ops.push_back(N->getOperand(2)); in SelectMVE_LongShift()
2624 Ops.push_back(getI32Imm(ImmValue, Loc)); // immediate shift count in SelectMVE_LongShift()
2626 Ops.push_back(N->getOperand(3)); in SelectMVE_LongShift()
2633 Ops.push_back(getI32Imm(SatBit, Loc)); in SelectMVE_LongShift()
2638 Ops.push_back(getAL(CurDAG, Loc)); in SelectMVE_LongShift()
2639 Ops.push_back(CurDAG->getRegister(0, MVT::i32)); in SelectMVE_LongShift()
2641 CurDAG->SelectNodeTo(N, Opcode, N->getVTList(), ArrayRef(Ops)); in SelectMVE_LongShift()
2648 SmallVector<SDValue, 8> Ops; in SelectMVE_VADCSBC() local
2654 Ops.push_back(N->getOperand(FirstInputOp)); in SelectMVE_VADCSBC()
2655 Ops.push_back(N->getOperand(FirstInputOp + 1)); in SelectMVE_VADCSBC()
2664 Ops.push_back(CarryIn); in SelectMVE_VADCSBC()
2669 AddMVEPredicateToOps(Ops, Loc, in SelectMVE_VADCSBC()
2673 AddEmptyMVEPredicateToOps(Ops, Loc, N->getValueType(0)); in SelectMVE_VADCSBC()
2675 CurDAG->SelectNodeTo(N, Opcode, N->getVTList(), ArrayRef(Ops)); in SelectMVE_VADCSBC()
2680 SmallVector<SDValue, 8> Ops; in SelectMVE_VSHLC() local
2684 Ops.push_back(N->getOperand(1)); in SelectMVE_VSHLC()
2685 Ops.push_back(N->getOperand(2)); in SelectMVE_VSHLC()
2687 Ops.push_back(getI32Imm(ImmValue, Loc)); // immediate shift count in SelectMVE_VSHLC()
2690 AddMVEPredicateToOps(Ops, Loc, N->getOperand(4)); in SelectMVE_VSHLC()
2692 AddEmptyMVEPredicateToOps(Ops, Loc); in SelectMVE_VSHLC()
2694 CurDAG->SelectNodeTo(N, ARM::MVE_VSHLC, N->getVTList(), ArrayRef(Ops)); in SelectMVE_VSHLC()
2738 SmallVector<SDValue, 8> Ops; in SelectBaseMVE_VMLLDAV() local
2741 Ops.push_back(N->getOperand(4)); in SelectBaseMVE_VMLLDAV()
2742 Ops.push_back(N->getOperand(5)); in SelectBaseMVE_VMLLDAV()
2745 Ops.push_back(N->getOperand(6)); in SelectBaseMVE_VMLLDAV()
2746 Ops.push_back(N->getOperand(7)); in SelectBaseMVE_VMLLDAV()
2749 AddMVEPredicateToOps(Ops, Loc, N->getOperand(8)); in SelectBaseMVE_VMLLDAV()
2751 AddEmptyMVEPredicateToOps(Ops, Loc); in SelectBaseMVE_VMLLDAV()
2753 CurDAG->SelectNodeTo(N, Opcode, N->getVTList(), ArrayRef(Ops)); in SelectBaseMVE_VMLLDAV()
2815 SDValue Ops[] = {Data, N->getOperand(PtrOperand), Chain}; in SelectMVE_VLD() local
2817 CurDAG->getMachineNode(OurOpcodes[Stage], Loc, ResultTys, Ops); in SelectMVE_VLD()
2825 SDValue Ops[] = {Data, N->getOperand(PtrOperand), Chain}; in SelectMVE_VLD() local
2827 CurDAG->getMachineNode(OurOpcodes[NumVecs - 1], Loc, ResultTys, Ops); in SelectMVE_VLD()
2861 SmallVector<SDValue, 8> Ops; in SelectMVE_VxDUP() local
2868 Ops.push_back(N->getOperand(OpIdx++)); // base in SelectMVE_VxDUP()
2870 Ops.push_back(N->getOperand(OpIdx++)); // limit in SelectMVE_VxDUP()
2874 Ops.push_back(getI32Imm(ImmValue, Loc)); in SelectMVE_VxDUP()
2877 AddMVEPredicateToOps(Ops, Loc, N->getOperand(OpIdx), Inactive); in SelectMVE_VxDUP()
2879 AddEmptyMVEPredicateToOps(Ops, Loc, N->getValueType(0)); in SelectMVE_VxDUP()
2881 CurDAG->SelectNodeTo(N, Opcode, N->getVTList(), ArrayRef(Ops)); in SelectMVE_VxDUP()
2888 SmallVector<SDValue, 8> Ops; in SelectCDE_CXxD() local
2895 Ops.push_back(getI32Imm(ImmCoprocVal, Loc)); in SelectCDE_CXxD()
2904 Ops.push_back(SDValue(createGPRPairNode(MVT::Untyped, AccLo, AccHi), 0)); in SelectCDE_CXxD()
2909 Ops.push_back(N->getOperand(OpIdx++)); in SelectCDE_CXxD()
2914 Ops.push_back(getI32Imm(ImmVal, Loc)); in SelectCDE_CXxD()
2920 Ops.push_back(Pred); in SelectCDE_CXxD()
2921 Ops.push_back(PredReg); in SelectCDE_CXxD()
2925 SDNode *InstrNode = CurDAG->getMachineNode(Opcode, Loc, MVT::Untyped, Ops); in SelectCDE_CXxD()
3014 SmallVector<SDValue, 6> Ops; in SelectVLDDup() local
3015 Ops.push_back(MemAddr); in SelectVLDDup()
3016 Ops.push_back(Align); in SelectVLDDup()
3026 Ops.push_back(Reg0); in SelectVLDDup()
3030 Ops.push_back(Inc); in SelectVLDDup()
3046 Ops.push_back(SDValue(VLdA, 0)); in SelectVLDDup()
3050 Ops.push_back(Pred); in SelectVLDDup()
3051 Ops.push_back(Reg0); in SelectVLDDup()
3052 Ops.push_back(Chain); in SelectVLDDup()
3054 SDNode *VLdDup = CurDAG->getMachineNode(Opc, dl, ResTys, Ops); in SelectVLDDup()
3244 SmallVector<SDValue, 3> Ops{ in transformFixedFloatingPointConversion() local
3246 AddEmptyMVEPredicateToOps(Ops, SDLoc(N), Type); in transformFixedFloatingPointConversion()
3267 ReplaceNode(N, CurDAG->getMachineNode(Opcode, SDLoc(N), Type, Ops)); in transformFixedFloatingPointConversion()
3304 SmallVector<SDValue, 3> Ops{Node->getOperand(0), in tryFP_TO_INT() local
3306 AddEmptyMVEPredicateToOps(Ops, dl, Type); in tryFP_TO_INT()
3308 ReplaceNode(N, CurDAG->getMachineNode(Opcode, dl, Type, Ops)); in tryFP_TO_INT()
3372 SDValue Ops[] = { N->getOperand(0).getOperand(0), in tryV6T2BitfieldExtractOp() local
3375 CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops); in tryV6T2BitfieldExtractOp()
3384 SDValue Ops[] = { N->getOperand(0).getOperand(0), ShOpc, in tryV6T2BitfieldExtractOp() local
3386 CurDAG->SelectNodeTo(N, ARM::MOVsi, MVT::i32, Ops); in tryV6T2BitfieldExtractOp()
3391 SDValue Ops[] = { N->getOperand(0).getOperand(0), in tryV6T2BitfieldExtractOp() local
3395 CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops); in tryV6T2BitfieldExtractOp()
3416 SDValue Ops[] = { N->getOperand(0).getOperand(0), in tryV6T2BitfieldExtractOp() local
3420 CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops); in tryV6T2BitfieldExtractOp()
3438 SDValue Ops[] = { N->getOperand(0).getOperand(0), in tryV6T2BitfieldExtractOp() local
3442 CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops); in tryV6T2BitfieldExtractOp()
3459 SDValue Ops[] = { N->getOperand(0).getOperand(0), in tryV6T2BitfieldExtractOp() local
3463 CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops); in tryV6T2BitfieldExtractOp()
3522 SDValue Ops[] = {N->getOperand(1), N->getOperand(2), N->getOperand(3), in SelectCMP_SWAP() local
3526 CurDAG->getVTList(MVT::i32, MVT::i32, MVT::Other), Ops); in SelectCMP_SWAP()
3578 SDValue Ops[] = { Src, CurDAG->getTargetConstant(Imm, dl, MVT::i32), in SelectCMPZ() local
3581 return CurDAG->getMachineNode(Opc, dl, MVT::i32, Ops); in SelectCMPZ()
3583 SDValue Ops[] = {CurDAG->getRegister(ARM::CPSR, MVT::i32), Src, in SelectCMPZ() local
3586 return CurDAG->getMachineNode(Opc, dl, MVT::i32, Ops); in SelectCMPZ()
3663 SDValue Ops[] = {ST->getValue(), in Select() local
3670 CurDAG->getMachineNode(ARM::tSTRspi, dl, MVT::Other, Ops); in Select()
3709 SDValue Ops[] = { in Select() local
3716 Ops); in Select()
3718 SDValue Ops[] = { in Select() local
3726 Ops); in Select()
3762 SDValue Ops[] = { TFI, CurDAG->getTargetConstant(0, dl, MVT::i32), in Select() local
3765 CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops); in Select()
3809 SDValue Ops[] = { V, V, ShImmOp, getAL(CurDAG, dl), Reg0, Reg0 }; in Select() local
3810 CurDAG->SelectNodeTo(N, ARM::t2ADDrs, MVT::i32, Ops); in Select()
3813 SDValue Ops[] = { V, V, Reg0, ShImmOp, getAL(CurDAG, dl), Reg0, in Select() local
3815 CurDAG->SelectNodeTo(N, ARM::ADDrsi, MVT::i32, Ops); in Select()
3828 SDValue Ops[] = { V, V, ShImmOp, getAL(CurDAG, dl), Reg0, Reg0 }; in Select() local
3829 CurDAG->SelectNodeTo(N, ARM::t2RSBrs, MVT::i32, Ops); in Select()
3832 SDValue Ops[] = { V, V, Reg0, ShImmOp, getAL(CurDAG, dl), Reg0, in Select() local
3834 CurDAG->SelectNodeTo(N, ARM::RSBrsi, MVT::i32, Ops); in Select()
3871 SDValue Ops[] = {CurDAG->getRegister(ARM::CPSR, MVT::i32), in Select() local
3874 ReplaceNode(N, CurDAG->getMachineNode(ARM::tBIC, dl, MVT::i32, Ops)); in Select()
3877 SDValue Ops[] = {N->getOperand(0), NewImm, getAL(CurDAG, dl), in Select() local
3881 CurDAG->getMachineNode(ARM::t2BICrr, dl, MVT::i32, Ops)); in Select()
3916 SDValue Ops[] = { N0.getOperand(0), Imm16, in Select() local
3918 ReplaceNode(N, CurDAG->getMachineNode(Opc, dl, VT, Ops)); in Select()
3927 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), in Select() local
3931 ReplaceNode(N, CurDAG->getMachineNode(Opc, dl, MVT::i32, MVT::i32, Ops)); in Select()
3936 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2), in Select() local
3940 N, CurDAG->getMachineNode(ARM::t2UMLAL, dl, MVT::i32, MVT::i32, Ops)); in Select()
3943 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2), in Select() local
3949 MVT::i32, MVT::i32, Ops)); in Select()
3955 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2), in Select() local
3959 N, CurDAG->getMachineNode(ARM::t2SMLAL, dl, MVT::i32, MVT::i32, Ops)); in Select()
3962 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2), in Select() local
3968 MVT::i32, MVT::i32, Ops)); in Select()
3996 SDValue Ops[] = { SmulLoHi.getOperand(0), SmulLoHi.getOperand(1), in Select() local
3999 ReplaceNode(N, CurDAG->getMachineNode(Opc, dl, MVT::i32, Ops)); in Select()
4037 SDValue Ops[] = { N->getOperand(1), in Select() local
4041 SDNode *New = CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops); in Select()
4061 SDValue Ops[] = {Base, RegOffset, ImmOffset, Chain}; in Select() local
4063 {MVT::Untyped, MVT::Other}, Ops); in Select()
4092 SDValue Ops[] = {SDValue(RegPair, 0), Base, RegOffset, ImmOffset, Chain}; in Select() local
4093 SDNode *New = CurDAG->getMachineNode(ARM::STOREDUAL, dl, MVT::Other, Ops); in Select()
4100 SDValue Ops[] = { N->getOperand(1), in Select() local
4105 CurDAG->getVTList(MVT::i32, MVT::Other), Ops); in Select()
4184 SDValue Ops[] = { N1, Tmp2, N3, Chain, InGlue }; in Select() local
4186 MVT::Glue, Ops); in Select()
4215 SDValue Ops[] = { X, CurDAG->getTargetConstant(Addend, dl, MVT::i32), in Select() local
4218 Add = CurDAG->getMachineNode(ARM::t2ADDri, dl, MVT::i32, Ops); in Select()
4221 SDValue Ops[] = {CurDAG->getRegister(ARM::CPSR, MVT::i32), X, in Select() local
4224 Add = CurDAG->getMachineNode(Opc, dl, MVT::i32, Ops); in Select()
4257 SDValue Ops[] = {N->getOperand(0), N->getOperand(1), NewARMcc, in Select() local
4259 CurDAG->MorphNodeTo(N, ARMISD::CMOV, N->getVTList(), Ops); in Select()
4274 SDValue Ops[] = {N->getOperand(0), N->getOperand(1), Pred, PredReg}; in Select() local
4275 ReplaceNode(N, CurDAG->getMachineNode(Opc, dl, VT, VT, Ops)); in Select()
4286 SDValue Ops[] = {N->getOperand(0), N->getOperand(1), Pred, PredReg}; in Select() local
4287 ReplaceNode(N, CurDAG->getMachineNode(Opc, dl, VT, VT, Ops)); in Select()
4297 SDValue Ops[] = {N->getOperand(0), N->getOperand(1), Pred, PredReg}; in Select() local
4298 ReplaceNode(N, CurDAG->getMachineNode(Opc, dl, VT, VT, Ops)); in Select()
4730 SmallVector<SDValue, 5> Ops; in Select() local
4731 Ops.push_back(getI32Imm(N->getConstantOperandVal(2), dl)); /* coproc */ in Select()
4732 Ops.push_back(getI32Imm(N->getConstantOperandVal(3), dl)); /* opc */ in Select()
4733 Ops.push_back(getI32Imm(N->getConstantOperandVal(4), dl)); /* CRm */ in Select()
4739 Ops.push_back(getAL(CurDAG, dl)); in Select()
4740 Ops.push_back(CurDAG->getRegister(0, MVT::i32)); in Select()
4743 Ops.push_back(Chain); in Select()
4748 ReplaceNode(N, CurDAG->getMachineNode(Opc, dl, RetType, Ops)); in Select()
4772 SDValue Ops[] = {MemAddr, getAL(CurDAG, dl), in Select() local
4774 SDNode *Ld = CurDAG->getMachineNode(NewOpc, dl, ResTys, Ops); in Select()
4825 SmallVector<SDValue, 7> Ops; in Select() local
4827 Ops.push_back(Val0); in Select()
4828 Ops.push_back(Val1); in Select()
4831 Ops.push_back(SDValue(createGPRPairNode(MVT::Untyped, Val0, Val1), 0)); in Select()
4832 Ops.push_back(MemAddr); in Select()
4833 Ops.push_back(getAL(CurDAG, dl)); in Select()
4834 Ops.push_back(CurDAG->getRegister(0, MVT::i32)); in Select()
4835 Ops.push_back(Chain); in Select()
4841 SDNode *St = CurDAG->getMachineNode(NewOpc, dl, ResTys, Ops); in Select()
5192 SDValue Ops[] = { Src, Src, Pred, Reg0 }; in Select() local
5193 CurDAG->SelectNodeTo(N, ARM::BF16_VCVTB, DestTy, Ops); in Select()
5203 SDValue Ops[] = { Src, Pred, Reg0 }; in Select() local
5204 CurDAG->SelectNodeTo(N, ARM::BF16_VCVT, MVT::v4bf16, Ops); in Select()
5372 std::vector<SDValue> &Ops) { in getIntOperandsFromRegisterString() argument
5383 Ops.push_back(CurDAG->getTargetConstant(IntField, DL, MVT::i32)); in getIntOperandsFromRegisterString()
5495 std::vector<SDValue> Ops; in tryReadRegister() local
5496 getIntOperandsFromRegisterString(RegString->getString(), CurDAG, DL, Ops); in tryReadRegister()
5498 if (!Ops.empty()) { in tryReadRegister()
5505 if (Ops.size() == 5){ in tryReadRegister()
5509 assert(Ops.size() == 3 && in tryReadRegister()
5515 Ops.push_back(getAL(CurDAG, DL)); in tryReadRegister()
5516 Ops.push_back(CurDAG->getRegister(0, MVT::i32)); in tryReadRegister()
5517 Ops.push_back(N->getOperand(0)); in tryReadRegister()
5518 ReplaceNode(N, CurDAG->getMachineNode(Opcode, DL, ResTypes, Ops)); in tryReadRegister()
5526 Ops = { CurDAG->getTargetConstant(BankedReg, DL, MVT::i32), in tryReadRegister()
5531 DL, MVT::i32, MVT::Other, Ops)); in tryReadRegister()
5556 Ops = { getAL(CurDAG, DL), CurDAG->getRegister(0, MVT::i32), in tryReadRegister()
5559 CurDAG->getMachineNode(Opcode, DL, MVT::i32, MVT::Other, Ops)); in tryReadRegister()
5571 SDValue Ops[] = { CurDAG->getTargetConstant(SYSmValue, DL, MVT::i32), in tryReadRegister() local
5575 N, CurDAG->getMachineNode(ARM::t2MRS_M, DL, MVT::i32, MVT::Other, Ops)); in tryReadRegister()
5582 Ops = { getAL(CurDAG, DL), CurDAG->getRegister(0, MVT::i32), in tryReadRegister()
5585 DL, MVT::i32, MVT::Other, Ops)); in tryReadRegister()
5590 Ops = { getAL(CurDAG, DL), CurDAG->getRegister(0, MVT::i32), in tryReadRegister()
5594 MVT::i32, MVT::Other, Ops)); in tryReadRegister()
5610 std::vector<SDValue> Ops; in tryWriteRegister() local
5611 getIntOperandsFromRegisterString(RegString->getString(), CurDAG, DL, Ops); in tryWriteRegister()
5613 if (!Ops.empty()) { in tryWriteRegister()
5619 if (Ops.size() == 5) { in tryWriteRegister()
5621 Ops.insert(Ops.begin()+2, N->getOperand(2)); in tryWriteRegister()
5623 assert(Ops.size() == 3 && in tryWriteRegister()
5627 Ops.insert(Ops.begin()+2, WriteValue, WriteValue+2); in tryWriteRegister()
5630 Ops.push_back(getAL(CurDAG, DL)); in tryWriteRegister()
5631 Ops.push_back(CurDAG->getRegister(0, MVT::i32)); in tryWriteRegister()
5632 Ops.push_back(N->getOperand(0)); in tryWriteRegister()
5634 ReplaceNode(N, CurDAG->getMachineNode(Opcode, DL, MVT::Other, Ops)); in tryWriteRegister()
5641 Ops = { CurDAG->getTargetConstant(BankedReg, DL, MVT::i32), N->getOperand(2), in tryWriteRegister()
5646 DL, MVT::Other, Ops)); in tryWriteRegister()
5664 Ops = { N->getOperand(2), getAL(CurDAG, DL), in tryWriteRegister()
5666 ReplaceNode(N, CurDAG->getMachineNode(Opcode, DL, MVT::Other, Ops)); in tryWriteRegister()
5682 SDValue Ops[] = { CurDAG->getTargetConstant(SYSmValue, DL, MVT::i32), in tryWriteRegister() local
5685 ReplaceNode(N, CurDAG->getMachineNode(ARM::t2MSR_M, DL, MVT::Other, Ops)); in tryWriteRegister()
5694 Ops = { CurDAG->getTargetConstant(Mask, DL, MVT::i32), N->getOperand(2), in tryWriteRegister()
5698 DL, MVT::Other, Ops)); in tryWriteRegister()
5808 std::vector<SDValue> Ops(GU->op_begin(), GU->op_end()-1); in tryInlineAsm() local
5809 Ops.push_back(T1.getValue(1)); in tryInlineAsm()
5810 CurDAG->UpdateNodeOperands(GU, Ops); in tryInlineAsm()