806       case ARM::R4:  in emitPrologue()
846       case ARM::R4:  in emitPrologue()
979       BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi16), ARM::R4)  in emitPrologue()
987       BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi16), ARM::R4)  in emitPrologue()
991       BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVTi16), ARM::R4)  in emitPrologue()
992           .addReg(ARM::R4)  in emitPrologue()
1007           .addReg(ARM::R4, RegState::Implicit)  in emitPrologue()
1018           .addReg(ARM::R4, RegState::Implicit)  in emitPrologue()
1026                 .addReg(ARM::R4, RegState::Kill)  in emitPrologue()
1139       case ARM::R4:  in emitPrologue()
1235       BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::R4)  in emitPrologue()
1238       emitAligningInstructions(MF, AFI, TII, MBB, MBBI, dl, ARM::R4, MaxAlign,  in emitPrologue()
1241           .addReg(ARM::R4, RegState::Kill)  in emitPrologue()
1356           assert(!MFI.getPristineRegs(MF).test(ARM::R4) &&  in emitEpilogue()
1358           emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::R4, FramePtr, -NumBytes,  in emitEpilogue()
1361               .addReg(ARM::R4)  in emitEpilogue()
1759   BuildMI(MBB, MI, DL, TII.get(Opc), ARM::R4)  in emitAlignedDPRCS2Spills()
1771   emitAligningInstructions(MF, AFI, TII, MBB, MI, DL, ARM::R4, MaxAlign, true);  in emitAlignedDPRCS2Spills()
1779                                 .addReg(ARM::R4)  in emitAlignedDPRCS2Spills()
1794     BuildMI(MBB, MI, DL, TII.get(ARM::VST1d64Qwb_fixed), ARM::R4)  in emitAlignedDPRCS2Spills()
1795         .addReg(ARM::R4, RegState::Kill)  in emitAlignedDPRCS2Spills()
1814         .addReg(ARM::R4)  in emitAlignedDPRCS2Spills()
1829         .addReg(ARM::R4)  in emitAlignedDPRCS2Spills()
1843         .addReg(ARM::R4)  in emitAlignedDPRCS2Spills()
1849   std::prev(MI)->addRegisterKilled(ARM::R4, TRI);  in emitAlignedDPRCS2Spills()
1876     assert(MI->killsRegister(ARM::R4) && "Missed kill flag");  in skipAlignedDPRCS2Spills()
1912   BuildMI(MBB, MI, DL, TII.get(Opc), ARM::R4)  in emitAlignedDPRCS2Restores()
1926         .addReg(ARM::R4, RegState::Define)  in emitAlignedDPRCS2Restores()
1927         .addReg(ARM::R4, RegState::Kill)  in emitAlignedDPRCS2Restores()
1944         .addReg(ARM::R4)  in emitAlignedDPRCS2Restores()
1957         .addReg(ARM::R4)  in emitAlignedDPRCS2Restores()
1967         .addReg(ARM::R4)  in emitAlignedDPRCS2Restores()
1972   std::prev(MI)->addRegisterKilled(ARM::R4, TRI);  in emitAlignedDPRCS2Restores()
2212   SavedRegs.set(ARM::R4);  in checkNumAlignedDPRCS2Regs()
2295     SavedRegs.set(ARM::R4);  in determineCalleeSaves()
2304     SavedRegs.set(ARM::R4);  in determineCalleeSaves()
2321       SavedRegs.set(ARM::R4);  in determineCalleeSaves()
2379       case ARM::R4: case ARM::R5:  in determineCalleeSaves()
2395       case ARM::R4: case ARM::R5:  in determineCalleeSaves()
2589       for (unsigned Reg : {ARM::R4, ARM::R5, ARM::R6}) {  in determineCalleeSaves()
3009   unsigned ScratchReg0 = ARM::R4;  in adjustForSegmentedStacks()