566   bool DstIsDead = MI.getOperand(OpIdx).isDead();  in ExpandVLD()  local
590     MIB.addReg(DstRegPair, RegState::Define | getDeadRegState(DstIsDead));  in ExpandVLD()
594     MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead));  in ExpandVLD()
596       MIB.addReg(D1, RegState::Define | getDeadRegState(DstIsDead));  in ExpandVLD()
598       MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead));  in ExpandVLD()
600       MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead));  in ExpandVLD()
662   MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead));  in ExpandVLD()
777   bool DstIsDead = false;  in ExpandLaneOp()  local
779     DstIsDead = MI.getOperand(OpIdx).isDead();  in ExpandLaneOp()
782     MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead));  in ExpandLaneOp()
784       MIB.addReg(D1, RegState::Define | getDeadRegState(DstIsDead));  in ExpandLaneOp()
786       MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead));  in ExpandLaneOp()
788       MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead));  in ExpandLaneOp()
830     MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead));  in ExpandLaneOp()
1000   bool DstIsDead = MI.getOperand(0).isDead();  in ExpandTMOV32BitImm()  local
1057   (--MBBI)->getOperand(0).setIsDead(DstIsDead);  in ExpandTMOV32BitImm()
1069   bool DstIsDead = MI.getOperand(0).isDead();  in ExpandMOV32BitImm()  local
1088           .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))  in ExpandMOV32BitImm()
1095           .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))  in ExpandMOV32BitImm()
1143                .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))  in ExpandMOV32BitImm()
1152     LO16->getOperand(0).setIsDead(DstIsDead);  in ExpandMOV32BitImm()
2606       bool DstIsDead = MI.getOperand(0).isDead();  in ExpandMI()  local
2613           .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))  in ExpandMI()
2628       bool DstIsDead = MI.getOperand(0).isDead();  in ExpandMI()  local
2672             .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))  in ExpandMI()
2689       bool DstIsDead = MI.getOperand(0).isDead();  in ExpandMI()  local
2714         .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))  in ExpandMI()
2766       bool DstIsDead = MI.getOperand(OpIdx).isDead();  in ExpandMI()  local
2779       MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead))  in ExpandMI()
2780         .addReg(D1, RegState::Define | getDeadRegState(DstIsDead));  in ExpandMI()
2783       MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead));  in ExpandMI()