Lines Matching refs:RegList
24 static const MCPhysReg RegList[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 }; in f64AssignAPCS() local
27 if (unsigned Reg = State.AllocateReg(RegList)) in f64AssignAPCS()
41 if (unsigned Reg = State.AllocateReg(RegList)) in f64AssignAPCS()
197 ArrayRef<MCPhysReg> RegList; in CC_ARM_AAPCS_Custom_Aggregate() local
200 RegList = RRegList; in CC_ARM_AAPCS_Custom_Aggregate()
201 unsigned RegIdx = State.getFirstUnallocated(RegList); in CC_ARM_AAPCS_Custom_Aggregate()
206 while (RegIdx % RegAlign != 0 && RegIdx < RegList.size()) in CC_ARM_AAPCS_Custom_Aggregate()
207 State.AllocateReg(RegList[RegIdx++]); in CC_ARM_AAPCS_Custom_Aggregate()
214 RegList = SRegList; in CC_ARM_AAPCS_Custom_Aggregate()
219 RegList = DRegList; in CC_ARM_AAPCS_Custom_Aggregate()
224 RegList = QRegList; in CC_ARM_AAPCS_Custom_Aggregate()
231 unsigned RegResult = State.AllocateRegBlock(RegList, PendingMembers.size()); in CC_ARM_AAPCS_Custom_Aggregate()
247 unsigned RegIdx = State.getFirstUnallocated(RegList); in CC_ARM_AAPCS_Custom_Aggregate()
249 if (RegIdx >= RegList.size()) in CC_ARM_AAPCS_Custom_Aggregate()
252 It.convertToReg(State.AllocateReg(RegList[RegIdx++])); in CC_ARM_AAPCS_Custom_Aggregate()
261 RegList = SRegList; in CC_ARM_AAPCS_Custom_Aggregate()
264 for (auto Reg : RegList) in CC_ARM_AAPCS_Custom_Aggregate()
289 ArrayRef<MCPhysReg> RegList) { in CustomAssignInRegList() argument
290 unsigned Reg = State.AllocateReg(RegList); in CustomAssignInRegList()