1104 ARMBaseInstrInfo::AddDReg(MachineInstrBuilder &MIB, unsigned Reg,  in AddDReg()  function in ARMBaseInstrInfo
1177           AddDReg(MIB, SrcReg, ARM::gsub_0, getKillRegState(isKill), TRI);  in storeRegToStackSlot()
1178           AddDReg(MIB, SrcReg, ARM::gsub_1, 0, TRI);  in storeRegToStackSlot()
1188           AddDReg(MIB, SrcReg, ARM::gsub_0, getKillRegState(isKill), TRI);  in storeRegToStackSlot()
1189           AddDReg(MIB, SrcReg, ARM::gsub_1, 0, TRI);  in storeRegToStackSlot()
1239           MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);  in storeRegToStackSlot()
1240           MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);  in storeRegToStackSlot()
1241           AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI);  in storeRegToStackSlot()
1271           MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);  in storeRegToStackSlot()
1272           MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);  in storeRegToStackSlot()
1273           MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI);  in storeRegToStackSlot()
1274                 AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI);  in storeRegToStackSlot()
1291         MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);  in storeRegToStackSlot()
1292         MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);  in storeRegToStackSlot()
1293         MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI);  in storeRegToStackSlot()
1294         MIB = AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI);  in storeRegToStackSlot()
1295         MIB = AddDReg(MIB, SrcReg, ARM::dsub_4, 0, TRI);  in storeRegToStackSlot()
1296         MIB = AddDReg(MIB, SrcReg, ARM::dsub_5, 0, TRI);  in storeRegToStackSlot()
1297         MIB = AddDReg(MIB, SrcReg, ARM::dsub_6, 0, TRI);  in storeRegToStackSlot()
1298               AddDReg(MIB, SrcReg, ARM::dsub_7, 0, TRI);  in storeRegToStackSlot()
1432         AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead, TRI);  in loadRegFromStackSlot()
1433         AddDReg(MIB, DestReg, ARM::gsub_1, RegState::DefineNoRead, TRI);  in loadRegFromStackSlot()
1443         MIB = AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead, TRI);  in loadRegFromStackSlot()
1444         MIB = AddDReg(MIB, DestReg, ARM::gsub_1, RegState::DefineNoRead, TRI);  in loadRegFromStackSlot()
1490         MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI);  in loadRegFromStackSlot()
1491         MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI);  in loadRegFromStackSlot()
1492         MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI);  in loadRegFromStackSlot()
1519          MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI);  in loadRegFromStackSlot()
1520          MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI);  in loadRegFromStackSlot()
1521          MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI);  in loadRegFromStackSlot()
1522          MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::DefineNoRead, TRI);  in loadRegFromStackSlot()
1540       MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI);  in loadRegFromStackSlot()
1541       MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI);  in loadRegFromStackSlot()
1542       MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI);  in loadRegFromStackSlot()
1543       MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::DefineNoRead, TRI);  in loadRegFromStackSlot()
1544       MIB = AddDReg(MIB, DestReg, ARM::dsub_4, RegState::DefineNoRead, TRI);  in loadRegFromStackSlot()
1545       MIB = AddDReg(MIB, DestReg, ARM::dsub_5, RegState::DefineNoRead, TRI);  in loadRegFromStackSlot()
1546       MIB = AddDReg(MIB, DestReg, ARM::dsub_6, RegState::DefineNoRead, TRI);  in loadRegFromStackSlot()
1547       MIB = AddDReg(MIB, DestReg, ARM::dsub_7, RegState::DefineNoRead, TRI);  in loadRegFromStackSlot()