Lines Matching refs:ARMBaseInstrInfo
115 ARMBaseInstrInfo::ARMBaseInstrInfo(const ARMSubtarget& STI) in ARMBaseInstrInfo() function in ARMBaseInstrInfo
129 ARMBaseInstrInfo::CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI, in CreateTargetHazardRecognizer()
142 ScheduleHazardRecognizer *ARMBaseInstrInfo::CreateTargetMIHazardRecognizer( in CreateTargetMIHazardRecognizer()
164 ScheduleHazardRecognizer *ARMBaseInstrInfo::
179 ARMBaseInstrInfo::convertToThreeAddress(MachineInstr &MI, LiveVariables *LV, in convertToThreeAddress()
355 bool ARMBaseInstrInfo::analyzeBranch(MachineBasicBlock &MBB, in analyzeBranch()
471 unsigned ARMBaseInstrInfo::removeBranch(MachineBasicBlock &MBB, in removeBranch()
498 unsigned ARMBaseInstrInfo::insertBranch(MachineBasicBlock &MBB, in insertBranch()
550 bool ARMBaseInstrInfo::
560 bool ARMBaseInstrInfo::isPredicated(const MachineInstr &MI) const { in isPredicated()
576 std::string ARMBaseInstrInfo::createMIROperandComment( in createMIROperandComment()
601 bool ARMBaseInstrInfo::PredicateInstruction( in PredicateInstruction()
635 bool ARMBaseInstrInfo::SubsumesPredicate(ArrayRef<MachineOperand> Pred1, in SubsumesPredicate()
661 bool ARMBaseInstrInfo::ClobbersPredicate(MachineInstr &MI, in ClobbersPredicate()
685 bool ARMBaseInstrInfo::isCPSRDefined(const MachineInstr &MI) { in isCPSRDefined()
717 return !ARMBaseInstrInfo::isCPSRDefined(*MI); in isEligibleForITBlock()
724 bool ARMBaseInstrInfo::isPredicable(const MachineInstr &MI) const { in isPredicable()
778 unsigned ARMBaseInstrInfo::getInstSizeInBytes(const MachineInstr &MI) const { in getInstSizeInBytes()
816 unsigned ARMBaseInstrInfo::getInstBundleLength(const MachineInstr &MI) const { in getInstBundleLength()
827 void ARMBaseInstrInfo::copyFromCPSR(MachineBasicBlock &MBB, in copyFromCPSR()
847 void ARMBaseInstrInfo::copyToCPSR(MachineBasicBlock &MBB, in copyToCPSR()
891 void ARMBaseInstrInfo::copyPhysReg(MachineBasicBlock &MBB, in copyPhysReg()
1058 ARMBaseInstrInfo::isCopyInstrImpl(const MachineInstr &MI) const { in isCopyInstrImpl()
1074 ARMBaseInstrInfo::describeLoadedValue(const MachineInstr &MI, in describeLoadedValue()
1104 ARMBaseInstrInfo::AddDReg(MachineInstrBuilder &MIB, unsigned Reg, in AddDReg()
1115 void ARMBaseInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB, in storeRegToStackSlot()
1307 unsigned ARMBaseInstrInfo::isStoreToStackSlot(const MachineInstr &MI, in isStoreToStackSlot()
1359 unsigned ARMBaseInstrInfo::isStoreToStackSlotPostFE(const MachineInstr &MI, in isStoreToStackSlotPostFE()
1372 void ARMBaseInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, in loadRegFromStackSlot()
1558 unsigned ARMBaseInstrInfo::isLoadFromStackSlot(const MachineInstr &MI, in isLoadFromStackSlot()
1616 unsigned ARMBaseInstrInfo::isLoadFromStackSlotPostFE(const MachineInstr &MI, in isLoadFromStackSlotPostFE()
1631 void ARMBaseInstrInfo::expandMEMCPY(MachineBasicBlock::iterator MI) const { in expandMEMCPY()
1634 const ARMBaseInstrInfo *TII = Subtarget.getInstrInfo(); in expandMEMCPY()
1685 bool ARMBaseInstrInfo::expandPostRAPseudo(MachineInstr &MI) const { in expandPostRAPseudo()
1808 void ARMBaseInstrInfo::reMaterialize(MachineBasicBlock &MBB, in reMaterialize()
1836 ARMBaseInstrInfo::duplicate(MachineBasicBlock &MBB, in duplicate()
1860 bool ARMBaseInstrInfo::produceSameValue(const MachineInstr &MI0, in produceSameValue()
1947 bool ARMBaseInstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, in areLoadsFromSameBasePtr()
2014 bool ARMBaseInstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, in shouldScheduleLoadsNear()
2044 bool ARMBaseInstrInfo::isSchedulingBoundary(const MachineInstr &MI, in isSchedulingBoundary()
2094 bool ARMBaseInstrInfo::
2120 bool ARMBaseInstrInfo::
2185 ARMBaseInstrInfo::extraSizeToPredicateInstructions(const MachineFunction &MF, in extraSizeToPredicateInstructions()
2199 ARMBaseInstrInfo::predictBranchSizeForIfCvt(MachineInstr &MI) const { in predictBranchSizeForIfCvt()
2222 ARMBaseInstrInfo::isProfitableToUnpredicate(MachineBasicBlock &TMBB, in isProfitableToUnpredicate()
2255 MachineInstr *ARMBaseInstrInfo::commuteInstructionImpl(MachineInstr &MI, in commuteInstructionImpl()
2284 ARMBaseInstrInfo::canFoldIntoMOVCC(Register Reg, const MachineRegisterInfo &MRI, in canFoldIntoMOVCC()
2318 bool ARMBaseInstrInfo::analyzeSelect(const MachineInstr &MI, in analyzeSelect()
2340 ARMBaseInstrInfo::optimizeSelect(MachineInstr &MI, in optimizeSelect()
2472 const ARMBaseInstrInfo &TII, in emitARMRegPlusImmediate()
2632 const ARMBaseInstrInfo &TII) { in rewriteARMFrameIndex()
2787 bool ARMBaseInstrInfo::analyzeCompare(const MachineInstr &MI, Register &SrcReg, in analyzeCompare()
3013 bool ARMBaseInstrInfo::optimizeCompareInstr( in optimizeCompareInstr()
3293 bool ARMBaseInstrInfo::shouldSink(const MachineInstr &MI) const { in shouldSink()
3311 bool ARMBaseInstrInfo::FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, in FoldImmediate()
3708 unsigned ARMBaseInstrInfo::getNumLDMAddresses(const MachineInstr &MI) const { in getNumLDMAddresses()
3762 unsigned ARMBaseInstrInfo::getNumMicroOps(const InstrItineraryData *ItinData, in getNumMicroOps()
3876 ARMBaseInstrInfo::getVLDMDefCycle(const InstrItineraryData *ItinData, in getVLDMDefCycle()
3916 ARMBaseInstrInfo::getLDMDefCycle(const InstrItineraryData *ItinData, in getLDMDefCycle()
3950 ARMBaseInstrInfo::getVSTMUseCycle(const InstrItineraryData *ItinData, in getVSTMUseCycle()
3989 ARMBaseInstrInfo::getSTMUseCycle(const InstrItineraryData *ItinData, in getSTMUseCycle()
4016 std::optional<unsigned> ARMBaseInstrInfo::getOperandLatency( in getOperandLatency()
4362 std::optional<unsigned> ARMBaseInstrInfo::getOperandLatency( in getOperandLatency()
4396 std::optional<unsigned> ARMBaseInstrInfo::getOperandLatencyImpl( in getOperandLatencyImpl()
4457 ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData, in getOperandLatency()
4715 unsigned ARMBaseInstrInfo::getPredicationCost(const MachineInstr &MI) const { in getPredicationCost()
4734 unsigned ARMBaseInstrInfo::getInstrLatency(const InstrItineraryData *ItinData, in getInstrLatency()
4785 unsigned ARMBaseInstrInfo::getInstrLatency(const InstrItineraryData *ItinData, in getInstrLatency()
4803 bool ARMBaseInstrInfo::hasHighOperandLatency(const TargetSchedModel &SchedModel, in hasHighOperandLatency()
4824 bool ARMBaseInstrInfo::hasLowDefLatency(const TargetSchedModel &SchedModel, in hasLowDefLatency()
4841 bool ARMBaseInstrInfo::verifyInstruction(const MachineInstr &MI, in verifyInstruction()
4912 void ARMBaseInstrInfo::expandLoadStackGuardBase(MachineBasicBlock::iterator MI, in expandLoadStackGuardBase()
5005 ARMBaseInstrInfo::isFpMLxInstruction(unsigned Opcode, unsigned &MulOpc, in isFpMLxInstruction()
5041 ARMBaseInstrInfo::getExecutionDomain(const MachineInstr &MI) const { in getExecutionDomain()
5131 void ARMBaseInstrInfo::setExecutionDomain(MachineInstr &MI, in setExecutionDomain()
5339 unsigned ARMBaseInstrInfo::getPartialRegUpdateClearance( in getPartialRegUpdateClearance()
5400 void ARMBaseInstrInfo::breakPartialRegDependency( in breakPartialRegDependency()
5433 bool ARMBaseInstrInfo::hasNOP() const { in hasNOP()
5437 bool ARMBaseInstrInfo::isSwiftFastImmShift(const MachineInstr *MI) const { in isSwiftFastImmShift()
5451 bool ARMBaseInstrInfo::getRegSequenceLikeInputs( in getRegSequenceLikeInputs()
5478 bool ARMBaseInstrInfo::getExtractSubregLikeInputs( in getExtractSubregLikeInputs()
5501 bool ARMBaseInstrInfo::getInsertSubregLikeInputs( in getInsertSubregLikeInputs()
5529 ARMBaseInstrInfo::decomposeMachineOperandsTargetFlags(unsigned TF) const { in decomposeMachineOperandsTargetFlags()
5535 ARMBaseInstrInfo::getSerializableDirectMachineOperandTargetFlags() const { in getSerializableDirectMachineOperandTargetFlags()
5547 ARMBaseInstrInfo::getSerializableBitmaskMachineOperandTargetFlags() const { in getSerializableBitmaskMachineOperandTargetFlags()
5561 ARMBaseInstrInfo::isAddImmediate(const MachineInstr &MI, Register Reg) const { in isAddImmediate()
5822 ARMBaseInstrInfo::findRegisterToSaveLRTo(outliner::Candidate &C) const { in findRegisterToSaveLRTo()
5874 ARMBaseInstrInfo::getOutliningCandidateInfo( in getOutliningCandidateInfo()
6092 bool ARMBaseInstrInfo::checkAndUpdateStackOffset(MachineInstr *MI, in checkAndUpdateStackOffset()
6195 void ARMBaseInstrInfo::mergeOutliningCandidateAttributes( in mergeOutliningCandidateAttributes()
6207 bool ARMBaseInstrInfo::isFunctionSafeToOutlineFrom( in isFunctionSafeToOutlineFrom()
6230 bool ARMBaseInstrInfo::isMBBSafeToOutlineFrom(MachineBasicBlock &MBB, in isMBBSafeToOutlineFrom()
6279 ARMBaseInstrInfo::getOutliningTypeImpl(MachineBasicBlock::iterator &MIT, in getOutliningTypeImpl()
6424 void ARMBaseInstrInfo::fixupPostOutline(MachineBasicBlock &MBB) const { in fixupPostOutline()
6430 void ARMBaseInstrInfo::saveLROnStack(MachineBasicBlock &MBB, in saveLROnStack()
6491 void ARMBaseInstrInfo::emitCFIForLRSaveToReg(MachineBasicBlock &MBB, in emitCFIForLRSaveToReg()
6506 void ARMBaseInstrInfo::restoreLRFromStack(MachineBasicBlock &MBB, in restoreLRFromStack()
6567 void ARMBaseInstrInfo::emitCFIForLRRestoreFromReg( in emitCFIForLRRestoreFromReg()
6580 void ARMBaseInstrInfo::buildOutlinedFrame( in buildOutlinedFrame()
6656 MachineBasicBlock::iterator ARMBaseInstrInfo::insertOutlinedCall( in insertOutlinedCall()
6720 bool ARMBaseInstrInfo::shouldOutlineFromFunctionByDefault( in shouldOutlineFromFunctionByDefault()
6725 bool ARMBaseInstrInfo::isReallyTriviallyReMaterializable( in isReallyTriviallyReMaterializable()
6974 ARMBaseInstrInfo::analyzeLoopForPipelining(MachineBasicBlock *LoopBB) const { in analyzeLoopForPipelining()