Lines Matching refs:AL
522 BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB).add(predOps(ARMCC::AL)); in insertBranch()
544 BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB).add(predOps(ARMCC::AL)); in insertBranch()
566 if (PIdx != -1 && I->getOperand(PIdx).getImm() != ARMCC::AL) in isPredicated()
573 return PIdx != -1 && MI.getOperand(PIdx).getImm() != ARMCC::AL; in isPredicated()
648 case ARMCC::AL: in SubsumesPredicate()
843 MIB.add(predOps(ARMCC::AL)) in copyFromCPSR()
863 .add(predOps(ARMCC::AL)) in copyToCPSR()
901 .add(predOps(ARMCC::AL)) in copyPhysReg()
929 MIB.add(predOps(ARMCC::AL)); in copyPhysReg()
994 .add(predOps(ARMCC::AL)); in copyPhysReg()
1000 .add(predOps(ARMCC::AL)); in copyPhysReg()
1006 .add(predOps(ARMCC::AL)); in copyPhysReg()
1012 .add(predOps(ARMCC::AL)); in copyPhysReg()
1046 Mov = Mov.add(predOps(ARMCC::AL)); in copyPhysReg()
1137 .add(predOps(ARMCC::AL)); in storeRegToStackSlot()
1148 .add(predOps(ARMCC::AL)); in storeRegToStackSlot()
1155 .add(predOps(ARMCC::AL)); in storeRegToStackSlot()
1162 .add(predOps(ARMCC::AL)); in storeRegToStackSlot()
1173 .add(predOps(ARMCC::AL)); in storeRegToStackSlot()
1180 .add(predOps(ARMCC::AL)); in storeRegToStackSlot()
1187 .add(predOps(ARMCC::AL)); in storeRegToStackSlot()
1203 .add(predOps(ARMCC::AL)); in storeRegToStackSlot()
1209 .add(predOps(ARMCC::AL)); in storeRegToStackSlot()
1232 .add(predOps(ARMCC::AL)); in storeRegToStackSlot()
1237 .add(predOps(ARMCC::AL)) in storeRegToStackSlot()
1259 .add(predOps(ARMCC::AL)); in storeRegToStackSlot()
1269 .add(predOps(ARMCC::AL)) in storeRegToStackSlot()
1289 .add(predOps(ARMCC::AL)) in storeRegToStackSlot()
1394 .add(predOps(ARMCC::AL)); in loadRegFromStackSlot()
1404 .add(predOps(ARMCC::AL)); in loadRegFromStackSlot()
1410 .add(predOps(ARMCC::AL)); in loadRegFromStackSlot()
1416 .add(predOps(ARMCC::AL)); in loadRegFromStackSlot()
1426 .add(predOps(ARMCC::AL)); in loadRegFromStackSlot()
1435 .add(predOps(ARMCC::AL)); in loadRegFromStackSlot()
1442 .add(predOps(ARMCC::AL)); in loadRegFromStackSlot()
1459 .add(predOps(ARMCC::AL)); in loadRegFromStackSlot()
1464 .add(predOps(ARMCC::AL)); in loadRegFromStackSlot()
1484 .add(predOps(ARMCC::AL)); in loadRegFromStackSlot()
1489 .add(predOps(ARMCC::AL)); in loadRegFromStackSlot()
1509 .add(predOps(ARMCC::AL)); in loadRegFromStackSlot()
1517 .add(predOps(ARMCC::AL)) in loadRegFromStackSlot()
1538 .add(predOps(ARMCC::AL)) in loadRegFromStackSlot()
1661 LDM.add(LDBase).add(predOps(ARMCC::AL)); in expandMEMCPY()
1664 STM.add(STBase).add(predOps(ARMCC::AL)); in expandMEMCPY()
1743 MIB.add(predOps(ARMCC::AL)); in expandPostRAPseudo()
2237 return ARMCC::AL; in getInstrPredicate()
2266 if (CC == ARMCC::AL || PredReg != ARM::CPSR) in commuteInstructionImpl()
2844 default: return ARMCC::AL; in getCmpToAddCondition()
3231 if (NewCC == ARMCC::AL) in optimizeCompareInstr()
3243 case ARMCC::AL: // none in optimizeCompareInstr()
3438 .add(predOps(ARMCC::AL)) in FoldImmediate()
4934 .add(predOps(ARMCC::AL)); in expandLoadStackGuardBase()
4946 .add(predOps(ARMCC::AL)) in expandLoadStackGuardBase()
4973 .add(predOps(ARMCC::AL)); in expandLoadStackGuardBase()
4979 .add(predOps(ARMCC::AL)); in expandLoadStackGuardBase()
4993 MIB.addMemOperand(MMO).add(predOps(ARMCC::AL)); in expandLoadStackGuardBase()
5001 .add(predOps(ARMCC::AL)); in expandLoadStackGuardBase()
5163 .add(predOps(ARMCC::AL)); in setExecutionDomain()
5186 .add(predOps(ARMCC::AL)); in setExecutionDomain()
5217 .add(predOps(ARMCC::AL)); in setExecutionDomain()
5252 .add(predOps(ARMCC::AL)); in setExecutionDomain()
5290 .add(predOps(ARMCC::AL)); in setExecutionDomain()
5308 .add(predOps(ARMCC::AL)); in setExecutionDomain()
5429 .add(predOps(ARMCC::AL)); in breakPartialRegDependency()
5619 if (Pred != ARMCC::AL || CmpMI->getOperand(1).getImm() != 0) in findCMPToFoldIntoCBZ()
6446 .add(predOps(ARMCC::AL)) in saveLROnStack()
6454 .add(predOps(ARMCC::AL)) in saveLROnStack()
6520 .add(predOps(ARMCC::AL)) in restoreLRFromStack()
6531 .add(predOps(ARMCC::AL)) in restoreLRFromStack()
6597 MIB.add(predOps(ARMCC::AL)); in buildOutlinedFrame()
6644 .add(predOps(ARMCC::AL)); in buildOutlinedFrame()
6673 MIB.add(predOps(ARMCC::AL)); in insertOutlinedCall()
6682 CallMIB.add(predOps(ARMCC::AL)); in insertOutlinedCall()
6817 .addImm(ARMCC::AL) in createTripCountGreaterCondition()