Lines Matching refs:DebugLoc
68 const DebugLoc &DL, unsigned Reg, unsigned Lane,
73 const DebugLoc &DL, unsigned DReg,
78 const DebugLoc &DL, unsigned Ssub0, unsigned Ssub1);
82 const DebugLoc &DL, unsigned Reg1,
87 const DebugLoc &DL, unsigned DReg,
92 const DebugLoc &DL);
415 const DebugLoc &DL, unsigned Reg, in createDupLane()
431 const DebugLoc &DL, unsigned DReg, unsigned Lane, in createExtractSubreg()
446 const DebugLoc &DL, unsigned Reg1, unsigned Reg2) { in createRegSequence()
463 const DebugLoc &DL, unsigned Ssub0, in createVExt()
476 const DebugLoc &DL, unsigned DReg, unsigned Lane, unsigned ToInsert) { in createInsertSubreg()
492 const DebugLoc &DL) { in createImplicitDef()
507 DebugLoc DL = MI->getDebugLoc(); in optimizeAllLanesPattern()