Lines Matching refs:TmpOffsetVGPR

1370   Register TmpOffsetVGPR;  in buildSpillLoadStore()  local
1396           .addReg(TmpOffsetVGPR);  in buildSpillLoadStore()
1399       assert(TmpOffsetVGPR);  in buildSpillLoadStore()
1438         TmpOffsetVGPR = RS->scavengeRegisterBackwards(AMDGPU::VGPR_32RegClass, MI, false, 0);  in buildSpillLoadStore()
1443             TmpOffsetVGPR = Reg;  in buildSpillLoadStore()
1449       assert(TmpOffsetVGPR);  in buildSpillLoadStore()
1480       MaterializeVOffset(ScratchOffsetReg, TmpOffsetVGPR, Offset);  in buildSpillLoadStore()
1522     if (UseVGPROffset && TmpOffsetVGPR == TmpIntermediateVGPR) {  in buildSpillLoadStore()
1529       MaterializeVOffset(ScratchOffsetReg, TmpOffsetVGPR, MaterializedOffset);  in buildSpillLoadStore()
1623       if (!TmpOffsetVGPR) {  in buildSpillLoadStore()
1624         TmpOffsetVGPR = RS->scavengeRegisterBackwards(AMDGPU::VGPR_32RegClass,  in buildSpillLoadStore()
1626         RS->setRegUsed(TmpOffsetVGPR);  in buildSpillLoadStore()
1642       MIB.addReg(TmpOffsetVGPR, getKillRegState(IsLastSubReg && !IsAGPR));  in buildSpillLoadStore()