Lines Matching refs:SB
1719 void SIRegisterInfo::buildVGPRSpillLoadStore(SGPRSpillBuilder &SB, int Index, in buildVGPRSpillLoadStore() argument
1723 MachineFrameInfo &FrameInfo = SB.MF.getFrameInfo(); in buildVGPRSpillLoadStore()
1727 FrameInfo.isFixedObjectIndex(Index) && hasBasePointer(SB.MF) in buildVGPRSpillLoadStore()
1729 : getFrameRegister(SB.MF); in buildVGPRSpillLoadStore()
1732 MachinePointerInfo PtrInfo = MachinePointerInfo::getFixedStack(SB.MF, Index); in buildVGPRSpillLoadStore()
1733 MachineMemOperand *MMO = SB.MF.getMachineMemOperand( in buildVGPRSpillLoadStore()
1735 SB.EltSize, Alignment); in buildVGPRSpillLoadStore()
1740 buildSpillLoadStore(*SB.MBB, SB.MI, SB.DL, Opc, Index, SB.TmpVGPR, false, in buildVGPRSpillLoadStore()
1741 FrameReg, Offset * SB.EltSize, MMO, SB.RS); in buildVGPRSpillLoadStore()
1745 buildSpillLoadStore(*SB.MBB, SB.MI, SB.DL, Opc, Index, SB.TmpVGPR, IsKill, in buildVGPRSpillLoadStore()
1746 FrameReg, Offset * SB.EltSize, MMO, SB.RS); in buildVGPRSpillLoadStore()
1748 SB.MFI.addToSpilledVGPRs(1); in buildVGPRSpillLoadStore()
1756 SGPRSpillBuilder SB(*this, *ST.getInstrInfo(), isWave32, MI, Index, RS); in spillSGPR() local
1759 SpillToPhysVGPRLane ? SB.MFI.getSGPRSpillToPhysicalVGPRLanes(Index) in spillSGPR()
1760 : SB.MFI.getSGPRSpillToVirtualVGPRLanes(Index); in spillSGPR()
1765 assert(SpillToVGPR || (SB.SuperReg != SB.MFI.getStackPtrOffsetReg() && in spillSGPR()
1766 SB.SuperReg != SB.MFI.getFrameOffsetReg())); in spillSGPR()
1770 assert(SB.NumSubRegs == VGPRSpills.size() && in spillSGPR()
1773 for (unsigned i = 0, e = SB.NumSubRegs; i < e; ++i) { in spillSGPR()
1775 SB.NumSubRegs == 1 in spillSGPR()
1776 ? SB.SuperReg in spillSGPR()
1777 : Register(getSubReg(SB.SuperReg, SB.SplitParts[i])); in spillSGPR()
1781 bool IsLastSubreg = i == SB.NumSubRegs - 1; in spillSGPR()
1782 bool UseKill = SB.IsKill && IsLastSubreg; in spillSGPR()
1787 auto MIB = BuildMI(*SB.MBB, MI, SB.DL, in spillSGPR()
1788 SB.TII.get(AMDGPU::SI_SPILL_S32_TO_VGPR), Spill.VGPR) in spillSGPR()
1799 if (IsFirstSubreg && SB.NumSubRegs > 1) { in spillSGPR()
1802 MIB.addReg(SB.SuperReg, RegState::ImplicitDefine); in spillSGPR()
1805 if (SB.NumSubRegs > 1 && (IsFirstSubreg || IsLastSubreg)) in spillSGPR()
1806 MIB.addReg(SB.SuperReg, getKillRegState(UseKill) | RegState::Implicit); in spillSGPR()
1813 SB.prepare(); in spillSGPR()
1816 unsigned SubKillState = getKillRegState((SB.NumSubRegs == 1) && SB.IsKill); in spillSGPR()
1819 auto PVD = SB.getPerVGPRData(); in spillSGPR()
1826 e = std::min((Offset + 1) * PVD.PerVGPR, SB.NumSubRegs); in spillSGPR()
1829 SB.NumSubRegs == 1 in spillSGPR()
1830 ? SB.SuperReg in spillSGPR()
1831 : Register(getSubReg(SB.SuperReg, SB.SplitParts[i])); in spillSGPR()
1834 BuildMI(*SB.MBB, MI, SB.DL, in spillSGPR()
1835 SB.TII.get(AMDGPU::SI_SPILL_S32_TO_VGPR), SB.TmpVGPR) in spillSGPR()
1838 .addReg(SB.TmpVGPR, TmpVGPRFlags); in spillSGPR()
1850 if (SB.NumSubRegs > 1) { in spillSGPR()
1853 if (i + 1 == SB.NumSubRegs) in spillSGPR()
1854 SuperKillState |= getKillRegState(SB.IsKill); in spillSGPR()
1855 WriteLane.addReg(SB.SuperReg, RegState::Implicit | SuperKillState); in spillSGPR()
1860 SB.readWriteTmpVGPR(Offset, /*IsLoad*/ false); in spillSGPR()
1863 SB.restore(); in spillSGPR()
1867 SB.MFI.addToSpilledSGPRs(SB.NumSubRegs); in spillSGPR()
1870 LIS->removeAllRegUnitsForPhysReg(SB.SuperReg); in spillSGPR()
1879 SGPRSpillBuilder SB(*this, *ST.getInstrInfo(), isWave32, MI, Index, RS); in restoreSGPR() local
1882 SpillToPhysVGPRLane ? SB.MFI.getSGPRSpillToPhysicalVGPRLanes(Index) in restoreSGPR()
1883 : SB.MFI.getSGPRSpillToVirtualVGPRLanes(Index); in restoreSGPR()
1889 for (unsigned i = 0, e = SB.NumSubRegs; i < e; ++i) { in restoreSGPR()
1891 SB.NumSubRegs == 1 in restoreSGPR()
1892 ? SB.SuperReg in restoreSGPR()
1893 : Register(getSubReg(SB.SuperReg, SB.SplitParts[i])); in restoreSGPR()
1896 auto MIB = BuildMI(*SB.MBB, MI, SB.DL, in restoreSGPR()
1897 SB.TII.get(AMDGPU::SI_RESTORE_S32_FROM_VGPR), SubReg) in restoreSGPR()
1900 if (SB.NumSubRegs > 1 && i == 0) in restoreSGPR()
1901 MIB.addReg(SB.SuperReg, RegState::ImplicitDefine); in restoreSGPR()
1910 SB.prepare(); in restoreSGPR()
1913 auto PVD = SB.getPerVGPRData(); in restoreSGPR()
1917 SB.readWriteTmpVGPR(Offset, /*IsLoad*/ true); in restoreSGPR()
1921 e = std::min((Offset + 1) * PVD.PerVGPR, SB.NumSubRegs); in restoreSGPR()
1924 SB.NumSubRegs == 1 in restoreSGPR()
1925 ? SB.SuperReg in restoreSGPR()
1926 : Register(getSubReg(SB.SuperReg, SB.SplitParts[i])); in restoreSGPR()
1929 auto MIB = BuildMI(*SB.MBB, MI, SB.DL, in restoreSGPR()
1930 SB.TII.get(AMDGPU::SI_RESTORE_S32_FROM_VGPR), SubReg) in restoreSGPR()
1931 .addReg(SB.TmpVGPR, getKillRegState(LastSubReg)) in restoreSGPR()
1933 if (SB.NumSubRegs > 1 && i == 0) in restoreSGPR()
1934 MIB.addReg(SB.SuperReg, RegState::ImplicitDefine); in restoreSGPR()
1944 SB.restore(); in restoreSGPR()
1950 LIS->removeAllRegUnitsForPhysReg(SB.SuperReg); in restoreSGPR()
1958 SGPRSpillBuilder SB(*this, *ST.getInstrInfo(), isWave32, MI, SGPR, false, 0, in spillEmergencySGPR() local
1960 SB.prepare(); in spillEmergencySGPR()
1962 unsigned SubKillState = getKillRegState((SB.NumSubRegs == 1) && SB.IsKill); in spillEmergencySGPR()
1963 auto PVD = SB.getPerVGPRData(); in spillEmergencySGPR()
1968 e = std::min((Offset + 1) * PVD.PerVGPR, SB.NumSubRegs); in spillEmergencySGPR()
1971 SB.NumSubRegs == 1 in spillEmergencySGPR()
1972 ? SB.SuperReg in spillEmergencySGPR()
1973 : Register(getSubReg(SB.SuperReg, SB.SplitParts[i])); in spillEmergencySGPR()
1976 BuildMI(*SB.MBB, MI, SB.DL, SB.TII.get(AMDGPU::V_WRITELANE_B32), in spillEmergencySGPR()
1977 SB.TmpVGPR) in spillEmergencySGPR()
1980 .addReg(SB.TmpVGPR, TmpVGPRFlags); in spillEmergencySGPR()
1984 if (SB.NumSubRegs > 1) { in spillEmergencySGPR()
1987 if (i + 1 == SB.NumSubRegs) in spillEmergencySGPR()
1988 SuperKillState |= getKillRegState(SB.IsKill); in spillEmergencySGPR()
1989 WriteLane.addReg(SB.SuperReg, RegState::Implicit | SuperKillState); in spillEmergencySGPR()
1997 SB.setMI(&RestoreMBB, MI); in spillEmergencySGPR()
2003 e = std::min((Offset + 1) * PVD.PerVGPR, SB.NumSubRegs); in spillEmergencySGPR()
2006 SB.NumSubRegs == 1 in spillEmergencySGPR()
2007 ? SB.SuperReg in spillEmergencySGPR()
2008 : Register(getSubReg(SB.SuperReg, SB.SplitParts[i])); in spillEmergencySGPR()
2010 auto MIB = BuildMI(*SB.MBB, MI, SB.DL, SB.TII.get(AMDGPU::V_READLANE_B32), in spillEmergencySGPR()
2012 .addReg(SB.TmpVGPR, getKillRegState(LastSubReg)) in spillEmergencySGPR()
2014 if (SB.NumSubRegs > 1 && i == 0) in spillEmergencySGPR()
2015 MIB.addReg(SB.SuperReg, RegState::ImplicitDefine); in spillEmergencySGPR()
2018 SB.restore(); in spillEmergencySGPR()
2020 SB.MFI.addToSpilledSGPRs(SB.NumSubRegs); in spillEmergencySGPR()