Lines Matching refs:iterator
217 void reportUnsupported(const MachineBasicBlock::iterator &MI,
233 constructFromMIWithMMO(const MachineBasicBlock::iterator &MI) const;
242 getLoadInfo(const MachineBasicBlock::iterator &MI) const;
247 getStoreInfo(const MachineBasicBlock::iterator &MI) const;
252 getAtomicFenceInfo(const MachineBasicBlock::iterator &MI) const;
257 getAtomicCmpxchgOrRmwInfo(const MachineBasicBlock::iterator &MI) const;
278 bool enableNamedBit(const MachineBasicBlock::iterator MI,
289 virtual bool enableLoadCacheBypass(const MachineBasicBlock::iterator &MI,
296 virtual bool enableStoreCacheBypass(const MachineBasicBlock::iterator &MI,
303 virtual bool enableRMWCacheBypass(const MachineBasicBlock::iterator &MI,
310 virtual bool enableVolatileAndOrNonTemporal(MachineBasicBlock::iterator &MI,
322 virtual bool insertWait(MachineBasicBlock::iterator &MI,
334 virtual bool insertAcquire(MachineBasicBlock::iterator &MI,
345 virtual bool insertRelease(MachineBasicBlock::iterator &MI,
355 MachineBasicBlock::iterator &MI) const { in tryForceStoreSC0SC1()
365 bool enableGLCBit(const MachineBasicBlock::iterator &MI) const { in enableGLCBit()
371 bool enableSLCBit(const MachineBasicBlock::iterator &MI) const { in enableSLCBit()
379 bool enableLoadCacheBypass(const MachineBasicBlock::iterator &MI,
383 bool enableStoreCacheBypass(const MachineBasicBlock::iterator &MI,
387 bool enableRMWCacheBypass(const MachineBasicBlock::iterator &MI,
391 bool enableVolatileAndOrNonTemporal(MachineBasicBlock::iterator &MI,
396 bool insertWait(MachineBasicBlock::iterator &MI,
403 bool insertAcquire(MachineBasicBlock::iterator &MI,
408 bool insertRelease(MachineBasicBlock::iterator &MI,
420 bool insertAcquire(MachineBasicBlock::iterator &MI,
432 bool enableLoadCacheBypass(const MachineBasicBlock::iterator &MI,
436 bool enableStoreCacheBypass(const MachineBasicBlock::iterator &MI,
440 bool enableRMWCacheBypass(const MachineBasicBlock::iterator &MI,
444 bool enableVolatileAndOrNonTemporal(MachineBasicBlock::iterator &MI,
449 bool insertWait(MachineBasicBlock::iterator &MI,
456 bool insertAcquire(MachineBasicBlock::iterator &MI,
461 bool insertRelease(MachineBasicBlock::iterator &MI,
473 bool enableSC0Bit(const MachineBasicBlock::iterator &MI) const { in enableSC0Bit()
479 bool enableSC1Bit(const MachineBasicBlock::iterator &MI) const { in enableSC1Bit()
485 bool enableNTBit(const MachineBasicBlock::iterator &MI) const { in enableNTBit()
493 bool enableLoadCacheBypass(const MachineBasicBlock::iterator &MI,
497 bool enableStoreCacheBypass(const MachineBasicBlock::iterator &MI,
501 bool enableRMWCacheBypass(const MachineBasicBlock::iterator &MI,
505 bool enableVolatileAndOrNonTemporal(MachineBasicBlock::iterator &MI,
510 bool insertAcquire(MachineBasicBlock::iterator &MI, SIAtomicScope Scope,
513 bool insertRelease(MachineBasicBlock::iterator &MI, SIAtomicScope Scope,
518 MachineBasicBlock::iterator &MI) const override { in tryForceStoreSC0SC1()
537 bool enableDLCBit(const MachineBasicBlock::iterator &MI) const { in enableDLCBit()
545 bool enableLoadCacheBypass(const MachineBasicBlock::iterator &MI,
549 bool enableVolatileAndOrNonTemporal(MachineBasicBlock::iterator &MI,
554 bool insertWait(MachineBasicBlock::iterator &MI,
561 bool insertAcquire(MachineBasicBlock::iterator &MI,
571 bool enableLoadCacheBypass(const MachineBasicBlock::iterator &MI,
575 bool enableVolatileAndOrNonTemporal(MachineBasicBlock::iterator &MI,
585 bool setTH(const MachineBasicBlock::iterator MI,
589 bool setScope(const MachineBasicBlock::iterator MI,
595 bool insertWait(MachineBasicBlock::iterator &MI, SIAtomicScope Scope,
599 bool insertAcquire(MachineBasicBlock::iterator &MI, SIAtomicScope Scope,
602 bool enableVolatileAndOrNonTemporal(MachineBasicBlock::iterator &MI,
615 std::list<MachineBasicBlock::iterator> AtomicPseudoMIs;
630 MachineBasicBlock::iterator &MI);
634 MachineBasicBlock::iterator &MI);
638 MachineBasicBlock::iterator &MI);
642 MachineBasicBlock::iterator &MI);
663 void SIMemOpAccess::reportUnsupported(const MachineBasicBlock::iterator &MI, in reportUnsupported()
724 const MachineBasicBlock::iterator &MI) const { in constructFromMIWithMMO()
784 SIMemOpAccess::getLoadInfo(const MachineBasicBlock::iterator &MI) const { in getLoadInfo()
798 SIMemOpAccess::getStoreInfo(const MachineBasicBlock::iterator &MI) const { in getStoreInfo()
812 SIMemOpAccess::getAtomicFenceInfo(const MachineBasicBlock::iterator &MI) const { in getAtomicFenceInfo()
845 const MachineBasicBlock::iterator &MI) const { in getAtomicCmpxchgOrRmwInfo()
864 bool SICacheControl::enableNamedBit(const MachineBasicBlock::iterator MI, in enableNamedBit()
893 const MachineBasicBlock::iterator &MI, in enableLoadCacheBypass()
928 const MachineBasicBlock::iterator &MI, in enableStoreCacheBypass()
941 const MachineBasicBlock::iterator &MI, in enableRMWCacheBypass()
956 MachineBasicBlock::iterator &MI, SIAtomicAddrSpace AddrSpace, SIMemOp Op, in enableVolatileAndOrNonTemporal()
1000 bool SIGfx6CacheControl::insertWait(MachineBasicBlock::iterator &MI, in insertWait()
1098 bool SIGfx6CacheControl::insertAcquire(MachineBasicBlock::iterator &MI, in insertAcquire()
1143 bool SIGfx6CacheControl::insertRelease(MachineBasicBlock::iterator &MI, in insertRelease()
1152 bool SIGfx7CacheControl::insertAcquire(MachineBasicBlock::iterator &MI, in insertAcquire()
1204 const MachineBasicBlock::iterator &MI, in enableLoadCacheBypass()
1246 const MachineBasicBlock::iterator &MI, in enableStoreCacheBypass()
1281 const MachineBasicBlock::iterator &MI, in enableRMWCacheBypass()
1309 MachineBasicBlock::iterator &MI, SIAtomicAddrSpace AddrSpace, SIMemOp Op, in enableVolatileAndOrNonTemporal()
1353 bool SIGfx90ACacheControl::insertWait(MachineBasicBlock::iterator &MI, in insertWait()
1381 bool SIGfx90ACacheControl::insertAcquire(MachineBasicBlock::iterator &MI, in insertAcquire()
1447 bool SIGfx90ACacheControl::insertRelease(MachineBasicBlock::iterator &MI, in insertRelease()
1498 const MachineBasicBlock::iterator &MI, SIAtomicScope Scope, in enableLoadCacheBypass()
1542 const MachineBasicBlock::iterator &MI, in enableStoreCacheBypass()
1582 const MachineBasicBlock::iterator &MI, SIAtomicScope Scope, in enableRMWCacheBypass()
1611 MachineBasicBlock::iterator &MI, SIAtomicAddrSpace AddrSpace, SIMemOp Op, in enableVolatileAndOrNonTemporal()
1650 bool SIGfx940CacheControl::insertAcquire(MachineBasicBlock::iterator &MI, in insertAcquire()
1736 bool SIGfx940CacheControl::insertRelease(MachineBasicBlock::iterator &MI, in insertRelease()
1800 const MachineBasicBlock::iterator &MI, in enableLoadCacheBypass()
1843 MachineBasicBlock::iterator &MI, SIAtomicAddrSpace AddrSpace, SIMemOp Op, in enableVolatileAndOrNonTemporal()
1893 bool SIGfx10CacheControl::insertWait(MachineBasicBlock::iterator &MI, in insertWait()
2014 bool SIGfx10CacheControl::insertAcquire(MachineBasicBlock::iterator &MI, in insertAcquire()
2070 const MachineBasicBlock::iterator &MI, SIAtomicScope Scope, in enableLoadCacheBypass()
2111 MachineBasicBlock::iterator &MI, SIAtomicAddrSpace AddrSpace, SIMemOp Op, in enableVolatileAndOrNonTemporal()
2164 bool SIGfx12CacheControl::setTH(const MachineBasicBlock::iterator MI, in setTH()
2179 bool SIGfx12CacheControl::setScope(const MachineBasicBlock::iterator MI, in setScope()
2194 bool SIGfx12CacheControl::insertWait(MachineBasicBlock::iterator &MI, in insertWait()
2290 bool SIGfx12CacheControl::insertAcquire(MachineBasicBlock::iterator &MI, in insertAcquire()
2347 MachineBasicBlock::iterator &MI, SIAtomicAddrSpace AddrSpace, SIMemOp Op, in enableVolatileAndOrNonTemporal()
2393 MachineBasicBlock::iterator &MI) { in expandLoad()
2438 MachineBasicBlock::iterator &MI) { in expandStore()
2471 MachineBasicBlock::iterator &MI) { in expandAtomicFence()
2518 MachineBasicBlock::iterator &MI) { in expandAtomicCmpxchgOrRmw()