44   LOAD = 1u << 0,  enumerator
967   assert(Op == SIMemOp::LOAD || Op == SIMemOp::STORE);  in enableVolatileAndOrNonTemporal()
975     if (Op == SIMemOp::LOAD)  in enableVolatileAndOrNonTemporal()
1148   return insertWait(MI, Scope, AddrSpace, SIMemOp::LOAD | SIMemOp::STORE,  in insertRelease()
1320   assert(Op == SIMemOp::LOAD || Op == SIMemOp::STORE);  in enableVolatileAndOrNonTemporal()
1328     if (Op == SIMemOp::LOAD)  in enableVolatileAndOrNonTemporal()
1622   assert(Op == SIMemOp::LOAD || Op == SIMemOp::STORE);  in enableVolatileAndOrNonTemporal()
1793   Changed |= insertWait(MI, Scope, AddrSpace, SIMemOp::LOAD | SIMemOp::STORE,  in insertRelease()
1855   assert(Op == SIMemOp::LOAD || Op == SIMemOp::STORE);  in enableVolatileAndOrNonTemporal()
1863     if (Op == SIMemOp::LOAD) {  in enableVolatileAndOrNonTemporal()
1916       if ((Op & SIMemOp::LOAD) != SIMemOp::NONE)  in insertWait()
1928         if ((Op & SIMemOp::LOAD) != SIMemOp::NONE)  in insertWait()
2123   assert(Op == SIMemOp::LOAD || Op == SIMemOp::STORE);  in enableVolatileAndOrNonTemporal()
2131     if (Op == SIMemOp::LOAD)  in enableVolatileAndOrNonTemporal()
2216       if ((Op & SIMemOp::LOAD) != SIMemOp::NONE)  in insertWait()
2228         if ((Op & SIMemOp::LOAD) != SIMemOp::NONE)  in insertWait()
2357   assert(Op == SIMemOp::LOAD || Op == SIMemOp::STORE);  in enableVolatileAndOrNonTemporal()
2409                                 SIMemOp::LOAD | SIMemOp::STORE,  in expandLoad()
2417                                 SIMemOp::LOAD,  in expandLoad()
2432                                                 SIMemOp::LOAD, MOI.isVolatile(),  in expandLoad()
2480                                 SIMemOp::LOAD | SIMemOp::STORE,  in expandAtomicFence()
2549                                 isAtomicRet(*MI) ? SIMemOp::LOAD :  in expandAtomicCmpxchgOrRmw()