34 static Register insertUndefLaneMask(MachineBasicBlock *MBB,
76                      MachineBasicBlock *MBB) override;
77   void buildMergeLaneMasks(MachineBasicBlock &MBB,
144   bool isSource(MachineBasicBlock &MBB) const {  in isSource()
145     return ReachableMap.find(&MBB)->second;  in isSource()
162       MachineBasicBlock *MBB = Incoming.Block;  in analyze()  local
163       if (MBB == &DefBlock) {  in analyze()
168       ReachableMap.try_emplace(MBB, false);  in analyze()
169       ReachableOrdered.push_back(MBB);  in analyze()
173       if (TII->hasDivergentBranch(MBB) && PDT.dominates(&DefBlock, MBB))  in analyze()
174         append_range(Stack, MBB->successors());  in analyze()
178       MachineBasicBlock *MBB = Stack.pop_back_val();  in analyze()  local
179       if (!ReachableMap.try_emplace(MBB, false).second)  in analyze()
181       ReachableOrdered.push_back(MBB);  in analyze()
183       append_range(Stack, MBB->successors());  in analyze()
186     for (MachineBasicBlock *MBB : ReachableOrdered) {  in analyze()
188       for (MachineBasicBlock *Pred : MBB->predecessors()) {  in analyze()
196         ReachableMap[MBB] = true;  in analyze()
269   void initialize(MachineBasicBlock &MBB) {  in initialize()  argument
277     DefBlock = &MBB;  in initialize()
330   bool inLoopLevel(MachineBasicBlock &MBB, unsigned LoopLevel,  in inLoopLevel()  argument
332     auto DomIt = Visited.find(&MBB);  in inLoopLevel()
337       if (Incoming.Block == &MBB)  in inLoopLevel()
368       MachineBasicBlock *MBB = Stack.pop_back_val();  in advanceLevel()  local
369       if (!PDT.dominates(VisitedPostDom, MBB))  in advanceLevel()
370         NextLevel.push_back(MBB);  in advanceLevel()
372       Visited[MBB] = Level;  in advanceLevel()
373       VisitedDom = DT.findNearestCommonDominator(VisitedDom, MBB);  in advanceLevel()
375       for (MachineBasicBlock *Succ : MBB->successors()) {  in advanceLevel()
377           if (MBB == VisitedPostDom)  in advanceLevel()
385           if (MBB == VisitedPostDom)  in advanceLevel()
419 static Register insertUndefLaneMask(MachineBasicBlock *MBB,  in insertUndefLaneMask()  argument
422   MachineFunction &MF = *MBB->getParent();  in insertUndefLaneMask()
426   BuildMI(*MBB, MBB->getFirstTerminator(), {}, TII->get(AMDGPU::IMPLICIT_DEF),  in insertUndefLaneMask()
469   for (MachineBasicBlock &MBB : *MF) {  in lowerCopiesFromI1()
470     for (MachineInstr &MI : MBB) {  in lowerCopiesFromI1()
492       BuildMI(MBB, MI, DL, TII->get(AMDGPU::V_CNDMASK_B32_e64), DstReg)  in lowerCopiesFromI1()
551     MachineBasicBlock &MBB = *MI->getParent();  in lowerPhis()  local
552     if (&MBB != PrevMBB) {  in lowerPhis()
553       LF.initialize(MBB);  in lowerPhis()
554       PrevMBB = &MBB;  in lowerPhis()
580     std::vector<MachineBasicBlock *> DomBlocks = {&MBB};  in lowerPhis()
613       PIA.analyze(MBB, Incomings);  in lowerPhis()
615       for (MachineBasicBlock *MBB : PIA.predecessors())  in lowerPhis()
617             MBB, insertUndefLaneMask(MBB, MRI, LaneMaskRegAttrs));  in lowerPhis()
641     Register NewReg = SSAUpdater.GetValueInMiddleOfBlock(&MBB);  in lowerPhis()
643       replaceDstReg(NewReg, DstReg, &MBB);  in lowerPhis()
658   for (MachineBasicBlock &MBB : *MF) {  in lowerCopiesToI1()
659     LF.initialize(MBB);  in lowerCopiesToI1()
661     for (MachineInstr &MI : MBB) {  in lowerCopiesToI1()
692         BuildMI(MBB, MI, DL, TII->get(AMDGPU::V_CMP_NE_U32_e64), TmpReg)  in lowerCopiesToI1()
704       std::vector<MachineBasicBlock *> DomBlocks = {&MBB};  in lowerCopiesToI1()
713         SSAUpdater.AddAvailableValue(&MBB, DstReg);  in lowerCopiesToI1()
716         buildMergeLaneMasks(MBB, MI, DL, DstReg,  in lowerCopiesToI1()
717                             SSAUpdater.GetValueInMiddleOfBlock(&MBB), SrcReg);  in lowerCopiesToI1()
782 PhiLoweringHelper::getSaluInsertionAtEnd(MachineBasicBlock &MBB) const {  in getSaluInsertionAtEnd()
783   auto InsertionPt = MBB.getFirstTerminator();  in getSaluInsertionAtEnd()
785   for (auto I = InsertionPt, E = MBB.end(); I != E; ++I) {  in getSaluInsertionAtEnd()
795   while (InsertionPt != MBB.begin()) {  in getSaluInsertionAtEnd()
815   for (MachineBasicBlock &MBB : *MF) {  in getCandidatesForLowering()
816     for (MachineInstr &MI : MBB.phis()) {  in getCandidatesForLowering()
846                                         MachineBasicBlock *MBB) {  in replaceDstReg()  argument
850 void Vreg1LoweringHelper::buildMergeLaneMasks(MachineBasicBlock &MBB,  in buildMergeLaneMasks()  argument
862       BuildMI(MBB, I, DL, TII->get(AMDGPU::COPY), DstReg).addReg(CurReg);  in buildMergeLaneMasks()
864       BuildMI(MBB, I, DL, TII->get(AMDGPU::COPY), DstReg).addReg(ExecReg);  in buildMergeLaneMasks()
866       BuildMI(MBB, I, DL, TII->get(XorOp), DstReg)  in buildMergeLaneMasks()
880       BuildMI(MBB, I, DL, TII->get(AndN2Op), PrevMaskedReg)  in buildMergeLaneMasks()
891       BuildMI(MBB, I, DL, TII->get(AndOp), CurMaskedReg)  in buildMergeLaneMasks()
898     BuildMI(MBB, I, DL, TII->get(AMDGPU::COPY), DstReg)  in buildMergeLaneMasks()
901     BuildMI(MBB, I, DL, TII->get(AMDGPU::COPY), DstReg)  in buildMergeLaneMasks()
904     BuildMI(MBB, I, DL, TII->get(OrN2Op), DstReg)  in buildMergeLaneMasks()
908     BuildMI(MBB, I, DL, TII->get(OrOp), DstReg)  in buildMergeLaneMasks()