Lines Matching refs:Incoming
74 SmallVectorImpl<Incoming> &Incomings) const override;
81 void constrainIncomingRegisterTakenAsIs(Incoming &In) override;
150 void analyze(MachineBasicBlock &DefBlock, ArrayRef<Incoming> Incomings) { in analyze()
161 for (auto Incoming : Incomings) { in analyze() local
162 MachineBasicBlock *MBB = Incoming.Block; in analyze()
308 ArrayRef<Incoming> Incomings = {}) { in addLoopEntries()
312 for (auto &Incoming : Incomings) local
313 Dom = DT.findNearestCommonDominator(Dom, Incoming.Block);
331 ArrayRef<Incoming> Incomings) const { in inLoopLevel()
336 for (auto &Incoming : Incomings) in inLoopLevel() local
337 if (Incoming.Block == &MBB) in inLoopLevel()
542 SmallVector<Incoming, 4> Incomings; in lowerPhis()
569 llvm::sort(Incomings, [this](Incoming LHS, Incoming RHS) { in lowerPhis()
599 for (auto &Incoming : Incomings) { in lowerPhis() local
600 Incoming.UpdatedReg = createLaneMaskReg(MRI, LaneMaskRegAttrs); in lowerPhis()
601 SSAUpdater.AddAvailableValue(Incoming.Block, Incoming.UpdatedReg); in lowerPhis()
604 for (auto &Incoming : Incomings) { in lowerPhis() local
605 MachineBasicBlock &IMBB = *Incoming.Block; in lowerPhis()
607 IMBB, getSaluInsertionAtEnd(IMBB), {}, Incoming.UpdatedReg, in lowerPhis()
608 SSAUpdater.GetValueInMiddleOfBlock(&IMBB), Incoming.Reg); in lowerPhis()
619 for (auto &Incoming : Incomings) { in lowerPhis() local
620 MachineBasicBlock &IMBB = *Incoming.Block; in lowerPhis()
622 constrainIncomingRegisterTakenAsIs(Incoming); in lowerPhis()
623 SSAUpdater.AddAvailableValue(&IMBB, Incoming.Reg); in lowerPhis()
625 Incoming.UpdatedReg = createLaneMaskReg(MRI, LaneMaskRegAttrs); in lowerPhis()
626 SSAUpdater.AddAvailableValue(&IMBB, Incoming.UpdatedReg); in lowerPhis()
630 for (auto &Incoming : Incomings) { in lowerPhis() local
631 if (!Incoming.UpdatedReg.isValid()) in lowerPhis()
634 MachineBasicBlock &IMBB = *Incoming.Block; in lowerPhis()
636 IMBB, getSaluInsertionAtEnd(IMBB), {}, Incoming.UpdatedReg, in lowerPhis()
637 SSAUpdater.GetValueInMiddleOfBlock(&IMBB), Incoming.Reg); in lowerPhis()
824 const MachineInstr *MI, SmallVectorImpl<Incoming> &Incomings) const { in collectIncomingValuesFromPhi()
914 void Vreg1LoweringHelper::constrainIncomingRegisterTakenAsIs(Incoming &In) { in constrainIncomingRegisterTakenAsIs()