69   void markAsLaneMask(Register DstReg) const override;
79                            Register DstReg, Register PrevReg,
474       Register DstReg = MI.getOperand(0).getReg();  in lowerCopiesFromI1()  local
479       if (isLaneMaskReg(DstReg) || isVreg1(DstReg))  in lowerCopiesFromI1()
488       assert(isVRegCompatibleReg(TII->getRegisterInfo(), *MRI, DstReg));  in lowerCopiesFromI1()
492       BuildMI(MBB, MI, DL, TII->get(AMDGPU::V_CNDMASK_B32_e64), DstReg)  in lowerCopiesFromI1()
559     Register DstReg = MI->getOperand(0).getReg();  in lowerPhis()  local
560     markAsLaneMask(DstReg);  in lowerPhis()
561     initializeLaneMaskRegisterAttributes(DstReg);  in lowerPhis()
575     PhiRegisters.insert(DstReg);  in lowerPhis()
581     for (MachineInstr &Use : MRI->use_instructions(DstReg))  in lowerPhis()
593     SSAUpdater.Initialize(DstReg);  in lowerPhis()
642     if (NewReg != DstReg) {  in lowerPhis()
643       replaceDstReg(NewReg, DstReg, &MBB);  in lowerPhis()
666       Register DstReg = MI.getOperand(0).getReg();  in lowerCopiesToI1()  local
667       if (!isVreg1(DstReg))  in lowerCopiesToI1()
672       if (MRI->use_empty(DstReg)) {  in lowerCopiesToI1()
679       markAsLaneMask(DstReg);  in lowerCopiesToI1()
680       initializeLaneMaskRegisterAttributes(DstReg);  in lowerCopiesToI1()
705       for (MachineInstr &Use : MRI->use_instructions(DstReg))  in lowerCopiesToI1()
712         SSAUpdater.Initialize(DstReg);  in lowerCopiesToI1()
713         SSAUpdater.AddAvailableValue(&MBB, DstReg);  in lowerCopiesToI1()
716         buildMergeLaneMasks(MBB, MI, DL, DstReg,  in lowerCopiesToI1()
809 void Vreg1LoweringHelper::markAsLaneMask(Register DstReg) const {  in markAsLaneMask()
810   MRI->setRegClass(DstReg, ST->getBoolRC());  in markAsLaneMask()
853                                               Register DstReg, Register PrevReg,  in buildMergeLaneMasks()  argument
862       BuildMI(MBB, I, DL, TII->get(AMDGPU::COPY), DstReg).addReg(CurReg);  in buildMergeLaneMasks()
864       BuildMI(MBB, I, DL, TII->get(AMDGPU::COPY), DstReg).addReg(ExecReg);  in buildMergeLaneMasks()
866       BuildMI(MBB, I, DL, TII->get(XorOp), DstReg)  in buildMergeLaneMasks()
898     BuildMI(MBB, I, DL, TII->get(AMDGPU::COPY), DstReg)  in buildMergeLaneMasks()
901     BuildMI(MBB, I, DL, TII->get(AMDGPU::COPY), DstReg)  in buildMergeLaneMasks()
904     BuildMI(MBB, I, DL, TII->get(OrN2Op), DstReg)  in buildMergeLaneMasks()
908     BuildMI(MBB, I, DL, TII->get(OrOp), DstReg)  in buildMergeLaneMasks()