112     unsigned Width;  member
769   Width = getOpcodeWidth(*I, *LSO.TII);  in setMI()
991     if (getBufferFormatWithCompCount(CI.Format, CI.Width + Paired.Width, STI) == 0)  in offsetsCanBeCombined()
1002     if (EltOffset0 + CI.Width != EltOffset1 &&  in offsetsCanBeCombined()
1003             EltOffset1 + Paired.Width != EltOffset0)  in offsetsCanBeCombined()
1014       if (CI.Width != Paired.Width &&  in offsetsCanBeCombined()
1015           (CI.Width < Paired.Width) == (CI.Offset < Paired.Offset))  in offsetsCanBeCombined()
1083   const unsigned Width = (CI.Width + Paired.Width);  in widthsFit()  local
1086     return (Width <= 4) && (STM.hasDwordx3LoadStores() || (Width != 3));  in widthsFit()
1090     switch (Width) {  in widthsFit()
1527       getBufferFormatWithCompCount(CI.Format, CI.Width + Paired.Width, *STM);  in mergeTBufferLoadPair()
1598       getBufferFormatWithCompCount(CI.Format, CI.Width + Paired.Width, *STM);  in mergeTBufferStorePair()
1706   const unsigned Width = CI.Width + Paired.Width;  in getNewOpcode()  local
1713                                   Width);  in getNewOpcode()
1717                                   Width);  in getNewOpcode()
1722     switch (Width) {  in getNewOpcode()
1735     switch (Width) {  in getNewOpcode()
1748     switch (Width) {  in getNewOpcode()
1761     switch (Width) {  in getNewOpcode()
1772     switch (Width) {  in getNewOpcode()
1783     switch (Width) {  in getNewOpcode()
1794     switch (Width) {  in getNewOpcode()
1805     switch (Width) {  in getNewOpcode()
1816     switch (Width) {  in getNewOpcode()
1827     assert(((unsigned)llvm::popcount(CI.DMask | Paired.DMask) == Width) &&  in getNewOpcode()
1829     return AMDGPU::getMaskedMIMGOp(CI.I->getOpcode(), Width);  in getNewOpcode()
1838            CI.Width + Paired.Width)) &&  in getSubRegIdxs()
1852   assert(CI.Width >= 1 && CI.Width <= 4);  in getSubRegIdxs()
1853   assert(Paired.Width >= 1 && Paired.Width <= 4);  in getSubRegIdxs()
1856     Idx1 = Idxs[0][Paired.Width - 1];  in getSubRegIdxs()
1857     Idx0 = Idxs[Paired.Width][CI.Width - 1];  in getSubRegIdxs()
1859     Idx0 = Idxs[0][CI.Width - 1];  in getSubRegIdxs()
1860     Idx1 = Idxs[CI.Width][Paired.Width - 1];  in getSubRegIdxs()
1871     switch (CI.Width + Paired.Width) {  in getTargetRegisterClass()
1887   unsigned BitWidth = 32 * (CI.Width + Paired.Width);  in getTargetRegisterClass()
2443       OptimizeListAgain |= CI.Width + Paired.Width < 8;  in optimizeInstsWithSameBaseAddr()
2447       OptimizeListAgain |= CI.Width + Paired.Width < 4;  in optimizeInstsWithSameBaseAddr()
2451       OptimizeListAgain |= CI.Width + Paired.Width < 4;  in optimizeInstsWithSameBaseAddr()
2455       OptimizeListAgain |= CI.Width + Paired.Width < 4;  in optimizeInstsWithSameBaseAddr()
2459       OptimizeListAgain |= CI.Width + Paired.Width < 4;  in optimizeInstsWithSameBaseAddr()
2463       OptimizeListAgain |= CI.Width + Paired.Width < 4;  in optimizeInstsWithSameBaseAddr()
2469       OptimizeListAgain |= CI.Width + Paired.Width < 4;  in optimizeInstsWithSameBaseAddr()
2475       OptimizeListAgain |= CI.Width + Paired.Width < 4;  in optimizeInstsWithSameBaseAddr()