202   const GCNSubtarget *STM = nullptr;  member in __anon56ab8fb50111::SILoadStoreOptimizer
750     EltSize = AMDGPU::convertSMRDOffsetUnits(*LSO.STM, 4);  in setMI()
1080 bool SILoadStoreOptimizer::widthsFit(const GCNSubtarget &STM,  in widthsFit()  argument
1086     return (Width <= 4) && (STM.hasDwordx3LoadStores() || (Width != 3));  in widthsFit()
1098       return STM.hasScalarDwordx3Loads();  in widthsFit()
1144     if (!widthsFit(*STM, CI, Paired) || !offsetsCanBeCombined(CI, *STM, Paired))  in checkAndPrepareMerge()
1174     offsetsCanBeCombined(CI, *STM, Paired, true);  in checkAndPrepareMerge()
1179   if (STM->ldsRequiresM0Init())  in read2Opcode()
1185   if (STM->ldsRequiresM0Init())  in read2ST64Opcode()
1274   if (STM->ldsRequiresM0Init())  in write2Opcode()
1281   if (STM->ldsRequiresM0Init())  in write2ST64Opcode()
1527       getBufferFormatWithCompCount(CI.Format, CI.Width + Paired.Width, *STM);  in mergeTBufferLoadPair()
1598       getBufferFormatWithCompCount(CI.Format, CI.Width + Paired.Width, *STM);  in mergeTBufferStorePair()
2187     static_cast<const SITargetLowering *>(STM->getTargetLowering());  in promoteConstantOffsetToImm()
2493   STM = &MF.getSubtarget<GCNSubtarget>();  in runOnMachineFunction()
2494   if (!STM->loadStoreOptEnabled())  in runOnMachineFunction()
2497   TII = STM->getInstrInfo();  in runOnMachineFunction()