116     InstClassEnum InstClass;  member
182       return (InstClass == MIMG) ? DMask < Other.DMask : Offset < Other.Offset;  in operator <()
611   assert(CI.InstClass == Paired.InstClass);  in getCommonInstClass()
613   if ((CI.InstClass == FLAT_LOAD || CI.InstClass == FLAT_STORE) &&  in getCommonInstClass()
615     return (CI.InstClass == FLAT_STORE) ? GLOBAL_STORE : GLOBAL_LOAD;  in getCommonInstClass()
617   return CI.InstClass;  in getCommonInstClass()
729   InstClass = getInstClass(Opc, *LSO.TII);  in setMI()
731   if (InstClass == UNKNOWN)  in setMI()
736   switch (InstClass) {  in setMI()
757   if (InstClass == MIMG) {  in setMI()
766   if (InstClass == TBUFFER_LOAD || InstClass == TBUFFER_STORE)  in setMI()
771   if ((InstClass == DS_READ) || (InstClass == DS_WRITE)) {  in setMI()
773   } else if (InstClass != MIMG) {  in setMI()
884   assert(CI.InstClass == MIMG);  in dmasksCanBeCombined()
960   assert(CI.InstClass != MIMG);  in offsetsCanBeCombined()
971   if (CI.InstClass == TBUFFER_LOAD || CI.InstClass == TBUFFER_STORE) {  in offsetsCanBeCombined()
1001   if ((CI.InstClass != DS_READ) && (CI.InstClass != DS_WRITE)) {  in offsetsCanBeCombined()
1007     if (CI.InstClass == S_LOAD_IMM || CI.InstClass == S_BUFFER_LOAD_IMM ||  in offsetsCanBeCombined()
1008         CI.InstClass == S_BUFFER_LOAD_SGPR_IMM) {  in offsetsCanBeCombined()
1084   switch (CI.InstClass) {  in widthsFit()
1130   if (CI.InstClass == UNKNOWN || Paired.InstClass == UNKNOWN)  in checkAndPrepareMerge()
1132   assert(CI.InstClass == Paired.InstClass);  in checkAndPrepareMerge()
1140   if (CI.InstClass == MIMG) {  in checkAndPrepareMerge()
1173   if (CI.InstClass == DS_READ || CI.InstClass == DS_WRITE)  in checkAndPrepareMerge()
1424   if (CI.InstClass == S_BUFFER_LOAD_SGPR_IMM)  in mergeSMemLoadImmPair()
1710     assert(CI.InstClass == BUFFER_LOAD || CI.InstClass == BUFFER_STORE);  in getNewOpcode()
1836   assert((CI.InstClass != MIMG ||  in getSubRegIdxs()
1869   if (CI.InstClass == S_BUFFER_LOAD_IMM ||  in getTargetRegisterClass()
1870       CI.InstClass == S_BUFFER_LOAD_SGPR_IMM || CI.InstClass == S_LOAD_IMM) {  in getTargetRegisterClass()
2261     if (AddrList.front().InstClass == CI.InstClass &&  in addInstToMergeableList()
2301     const InstClassEnum InstClass = getInstClass(MI.getOpcode(), *TII);  in collectMergeableInsts()  local
2302     if (InstClass == UNKNOWN)  in collectMergeableInsts()
2318     if (CI.InstClass == DS_WRITE && CI.IsAGPR) {  in collectMergeableInsts()
2429     switch (CI.InstClass) {  in optimizeInstsWithSameBaseAddr()