7735   const TargetRegisterClass *Src1SubRC =  in splitScalarSMulU64()  local
7737   if (RI.isSGPRClass(Src1SubRC))  in splitScalarSMulU64()
7738     Src1SubRC = RI.getEquivalentVGPRClass(Src1SubRC);  in splitScalarSMulU64()
7745       buildExtractSubRegOrImm(MII, MRI, Src1, Src1RC, AMDGPU::sub0, Src1SubRC);  in splitScalarSMulU64()
7749       buildExtractSubRegOrImm(MII, MRI, Src1, Src1RC, AMDGPU::sub1, Src1SubRC);  in splitScalarSMulU64()
7844   const TargetRegisterClass *Src1SubRC =  in splitScalarSMulPseudo()  local
7846   if (RI.isSGPRClass(Src1SubRC))  in splitScalarSMulPseudo()
7847     Src1SubRC = RI.getEquivalentVGPRClass(Src1SubRC);  in splitScalarSMulPseudo()
7854       buildExtractSubRegOrImm(MII, MRI, Src1, Src1RC, AMDGPU::sub0, Src1SubRC);  in splitScalarSMulPseudo()
7909   const TargetRegisterClass *Src1SubRC =  in splitScalar64BitBinaryOp()  local
7915                                                        AMDGPU::sub0, Src1SubRC);  in splitScalar64BitBinaryOp()
7919                                                        AMDGPU::sub1, Src1SubRC);  in splitScalar64BitBinaryOp()