66 SIInstrInfo::SIInstrInfo(const GCNSubtarget &ST)  in SIInstrInfo()  function in SIInstrInfo
112   if (SIInstrInfo::isVOP1(MI) || SIInstrInfo::isVOP2(MI) ||  in canRemat()
113       SIInstrInfo::isVOP3(MI) || SIInstrInfo::isSDWA(MI) ||  in canRemat()
114       SIInstrInfo::isSALU(MI))  in canRemat()
117   if (SIInstrInfo::isSMRD(MI)) {  in canRemat()
127 bool SIInstrInfo::isReallyTriviallyReMaterializable(  in isReallyTriviallyReMaterializable()
187 bool SIInstrInfo::isIgnorableUse(const MachineOperand &MO) const {  in isIgnorableUse()
193 bool SIInstrInfo::isSafeToSink(MachineInstr &MI,  in isSafeToSink()
235 bool SIInstrInfo::areLoadsFromSameBasePtr(SDNode *Load0, SDNode *Load1,  in areLoadsFromSameBasePtr()
361 bool SIInstrInfo::getMemOperandsWithOffsetWidth(  in getMemOperandsWithOffsetWidth()
550 bool SIInstrInfo::shouldClusterMemOps(ArrayRef<const MachineOperand *> BaseOps1,  in shouldClusterMemOps()
595 bool SIInstrInfo::shouldScheduleLoadsNear(SDNode *Load0, SDNode *Load1,  in shouldScheduleLoadsNear()
607 static void reportIllegalCopy(const SIInstrInfo *TII, MachineBasicBlock &MBB,  in reportIllegalCopy()
624 static void indirectCopyToAGPR(const SIInstrInfo &TII,  in indirectCopyToAGPR()
743 static void expandSGPRCopy(const SIInstrInfo &TII, MachineBasicBlock &MBB,  in expandSGPRCopy()
795 void SIInstrInfo::copyPhysReg(MachineBasicBlock &MBB,  in copyPhysReg()
1148 int SIInstrInfo::commuteOpcode(unsigned Opcode) const {  in commuteOpcode()
1166 void SIInstrInfo::materializeImmediate(MachineBasicBlock &MBB,  in materializeImmediate()
1223 SIInstrInfo::getPreferredSelectRegClass(unsigned Size) const {  in getPreferredSelectRegClass()
1227 void SIInstrInfo::insertVectorSelect(MachineBasicBlock &MBB,  in insertVectorSelect()
1252     case SIInstrInfo::SCC_TRUE: {  in insertVectorSelect()
1266     case SIInstrInfo::SCC_FALSE: {  in insertVectorSelect()
1280     case SIInstrInfo::VCCNZ: {  in insertVectorSelect()
1294     case SIInstrInfo::VCCZ: {  in insertVectorSelect()
1308     case SIInstrInfo::EXECNZ: {  in insertVectorSelect()
1326     case SIInstrInfo::EXECZ: {  in insertVectorSelect()
1353 Register SIInstrInfo::insertEQ(MachineBasicBlock *MBB,  in insertEQ()
1366 Register SIInstrInfo::insertNE(MachineBasicBlock *MBB,  in insertNE()
1379 unsigned SIInstrInfo::getMovOpcode(const TargetRegisterClass *DstRC) const {  in getMovOpcode()
1398 SIInstrInfo::getIndirectGPRIDXPseudo(unsigned VecSize,  in getIndirectGPRIDXPseudo()
1531 SIInstrInfo::getIndirectRegWriteMovRelPseudo(unsigned VecSize, unsigned EltSize,  in getIndirectRegWriteMovRelPseudo()
1718 void SIInstrInfo::storeRegToStackSlot(  in storeRegToStackSlot()
1943 void SIInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,  in loadRegFromStackSlot()
1995 void SIInstrInfo::insertNoop(MachineBasicBlock &MBB,  in insertNoop()
2000 void SIInstrInfo::insertNoops(MachineBasicBlock &MBB,  in insertNoops()
2011 void SIInstrInfo::insertReturn(MachineBasicBlock &MBB) const {  in insertReturn()
2029 unsigned SIInstrInfo::getNumWaitStates(const MachineInstr &MI) {  in getNumWaitStates()
2043 bool SIInstrInfo::expandPostRAPseudo(MachineInstr &MI) const {  in expandPostRAPseudo()
2509 void SIInstrInfo::reMaterialize(MachineBasicBlock &MBB,  in reMaterialize()
2596 SIInstrInfo::expandMovDPP64(MachineInstr &MI) const {  in expandMovDPP64()
2660 SIInstrInfo::isCopyInstrImpl(const MachineInstr &MI) const {  in isCopyInstrImpl()
2667 bool SIInstrInfo::swapSourceModifiers(MachineInstr &MI,  in swapSourceModifiers()
2717 MachineInstr *SIInstrInfo::commuteInstructionImpl(MachineInstr &MI, bool NewMI,  in commuteInstructionImpl()
2772 bool SIInstrInfo::findCommutedOpIndices(const MachineInstr &MI,  in findCommutedOpIndices()
2778 bool SIInstrInfo::findCommutedOpIndices(const MCInstrDesc &Desc,  in findCommutedOpIndices()
2796 bool SIInstrInfo::isBranchOffsetInRange(unsigned BranchOp,  in isBranchOffsetInRange()
2813 SIInstrInfo::getBranchDestBlock(const MachineInstr &MI) const {  in getBranchDestBlock()
2817 bool SIInstrInfo::hasDivergentBranch(const MachineBasicBlock *MBB) const {  in hasDivergentBranch()
2827 void SIInstrInfo::insertIndirectBranch(MachineBasicBlock &MBB,  in insertIndirectBranch()
2945 unsigned SIInstrInfo::getBranchOpcode(SIInstrInfo::BranchPredicate Cond) {  in getBranchOpcode()
2947   case SIInstrInfo::SCC_TRUE:  in getBranchOpcode()
2949   case SIInstrInfo::SCC_FALSE:  in getBranchOpcode()
2951   case SIInstrInfo::VCCNZ:  in getBranchOpcode()
2953   case SIInstrInfo::VCCZ:  in getBranchOpcode()
2955   case SIInstrInfo::EXECNZ:  in getBranchOpcode()
2957   case SIInstrInfo::EXECZ:  in getBranchOpcode()
2964 SIInstrInfo::BranchPredicate SIInstrInfo::getBranchPredicate(unsigned Opcode) {  in getBranchPredicate()
2983 bool SIInstrInfo::analyzeBranchImpl(MachineBasicBlock &MBB,  in analyzeBranchImpl()
3026 bool SIInstrInfo::analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,  in analyzeBranch()
3071 unsigned SIInstrInfo::removeBranch(MachineBasicBlock &MBB,  in removeBranch()
3097 unsigned SIInstrInfo::insertBranch(MachineBasicBlock &MBB,  in insertBranch()
3156 bool SIInstrInfo::reverseBranchCondition(  in reverseBranchCondition()
3170 bool SIInstrInfo::canInsertSelect(const MachineBasicBlock &MBB,  in canInsertSelect()
3212 void SIInstrInfo::insertSelect(MachineBasicBlock &MBB,  in insertSelect()
3319 bool SIInstrInfo::isFoldableCopy(const MachineInstr &MI) {  in isFoldableCopy()
3345 void SIInstrInfo::removeModOperands(MachineInstr &MI) const {  in removeModOperands()
3354 bool SIInstrInfo::FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI,  in FoldImmediate()
3646 bool SIInstrInfo::checkInstOffsetsDoNotOverlap(const MachineInstr &MIa,  in checkInstOffsetsDoNotOverlap()
3670 bool SIInstrInfo::areMemAccessesTriviallyDisjoint(const MachineInstr &MIa,  in areMemAccessesTriviallyDisjoint()
3739   if (Def && SIInstrInfo::isFoldableCopy(*Def) && Def->getOperand(1).isImm()) {  in getFoldableImm()
3769 MachineInstr *SIInstrInfo::convertToThreeAddress(MachineInstr &MI,  in convertToThreeAddress()
3788   if (SIInstrInfo::isWMMA(MI)) {  in convertToThreeAddress()
4001 bool SIInstrInfo::isSchedulingBoundary(const MachineInstr &MI,  in isSchedulingBoundary()
4032 bool SIInstrInfo::isAlwaysGDS(uint16_t Opcode) const {  in isAlwaysGDS()
4036 bool SIInstrInfo::modifiesModeRegister(const MachineInstr &MI) {  in modifiesModeRegister()
4043 bool SIInstrInfo::hasUnwantedEffectsWhenEXECEmpty(const MachineInstr &MI) const {  in hasUnwantedEffectsWhenEXECEmpty()
4086 bool SIInstrInfo::mayReadEXEC(const MachineRegisterInfo &MRI,  in mayReadEXEC()
4111 bool SIInstrInfo::isInlineConstant(const APInt &Imm) const {  in isInlineConstant()
4131 bool SIInstrInfo::isInlineConstant(const MachineOperand &MO,  in isInlineConstant()
4242 bool SIInstrInfo::isImmOperandLegal(const MachineInstr &MI, unsigned OpNo,  in isImmOperandLegal()
4272 bool SIInstrInfo::hasVALU32BitEncoding(unsigned Opcode) const {  in hasVALU32BitEncoding()
4284 bool SIInstrInfo::hasModifiers(unsigned Opcode) const {  in hasModifiers()
4291 bool SIInstrInfo::hasModifiersSet(const MachineInstr &MI,  in hasModifiersSet()
4297 bool SIInstrInfo::hasAnyModifiersSet(const MachineInstr &MI) const {  in hasAnyModifiersSet()
4302 bool SIInstrInfo::canShrink(const MachineInstr &MI,  in canShrink()
4372 MachineInstr *SIInstrInfo::buildShrunkInst(MachineInstr &MI,  in buildShrunkInst()
4418 bool SIInstrInfo::usesConstantBus(const MachineRegisterInfo &MRI,  in usesConstantBus()
4469   if (SIInstrInfo::isVALU(MI)) {  in shouldReadExec()
4482       SIInstrInfo::isGenericOpcode(MI.getOpcode()) ||  in shouldReadExec()
4483       SIInstrInfo::isSALU(MI) ||  in shouldReadExec()
4484       SIInstrInfo::isSMRD(MI))  in shouldReadExec()
4500 bool SIInstrInfo::verifyInstruction(const MachineInstr &MI,  in verifyInstruction()
4503   if (SIInstrInfo::isGenericOpcode(MI.getOpcode()))  in verifyInstruction()
5214 unsigned SIInstrInfo::getVALUOp(const MachineInstr &MI) const {  in getVALUOp()
5375 void SIInstrInfo::insertScratchExecCopy(MachineFunction &MF,  in insertScratchExecCopy()
5382   const SIInstrInfo *TII = ST.getInstrInfo();  in insertScratchExecCopy()
5408 void SIInstrInfo::restoreExec(MachineFunction &MF, MachineBasicBlock &MBB,  in restoreExec()
5456 const TargetRegisterClass *SIInstrInfo::getRegClass(const MCInstrDesc &TID,  in getRegClass()
5486 const TargetRegisterClass *SIInstrInfo::getOpRegClass(const MachineInstr &MI,  in getOpRegClass()
5503 void SIInstrInfo::legalizeOpWithMove(MachineInstr &MI, unsigned OpIdx) const {  in legalizeOpWithMove()
5524 unsigned SIInstrInfo::buildExtractSubReg(  in buildExtractSubReg()
5553 MachineOperand SIInstrInfo::buildExtractSubRegOrImm(  in buildExtractSubRegOrImm()
5572 void SIInstrInfo::swapOperands(MachineInstr &Inst) const {  in swapOperands()
5579 bool SIInstrInfo::isLegalRegOperand(const MachineRegisterInfo &MRI,  in isLegalRegOperand()
5606 bool SIInstrInfo::isLegalVSrcOperand(const MachineRegisterInfo &MRI,  in isLegalVSrcOperand()
5617 bool SIInstrInfo::isOperandLegal(const MachineInstr &MI, unsigned OpIdx,  in isOperandLegal()
5732 void SIInstrInfo::legalizeOperandsVOP2(MachineRegisterInfo &MRI,  in legalizeOperandsVOP2()
5850 void SIInstrInfo::legalizeOperandsVOP3(MachineRegisterInfo &MRI,  in legalizeOperandsVOP3()
5941 Register SIInstrInfo::readlaneVGPRToSGPR(Register SrcReg, MachineInstr &UseMI,  in readlaneVGPRToSGPR()
5983 void SIInstrInfo::legalizeOperandsSMRD(MachineRegisterInfo &MRI,  in legalizeOperandsSMRD()
6002 bool SIInstrInfo::moveFlatAddrToVGPR(MachineInstr &Inst) const {  in moveFlatAddrToVGPR()
6083 void SIInstrInfo::legalizeOperandsFLAT(MachineRegisterInfo &MRI,  in legalizeOperandsFLAT()
6101 void SIInstrInfo::legalizeGenericOperand(MachineBasicBlock &InsertMBB,  in legalizeGenericOperand()
6147     const SIInstrInfo &TII, MachineRegisterInfo &MRI, MachineBasicBlock &OrigBB,  in emitLoadScalarOpsFromVGPRLoop()
6289 loadMBUFScalarOperandsFromVGPR(const SIInstrInfo &TII, MachineInstr &MI,  in loadMBUFScalarOperandsFromVGPR()
6391 extractRsrcPtr(const SIInstrInfo &TII, MachineInstr &MI, MachineOperand &Rsrc) {  in extractRsrcPtr()
6433 SIInstrInfo::legalizeOperands(MachineInstr &MI,  in legalizeOperands()
6828 void SIInstrInfo::moveToVALU(SIInstrWorklist &Worklist,  in moveToVALU()
6849 void SIInstrInfo::moveToVALUImpl(SIInstrWorklist &Worklist,  in moveToVALUImpl()
7384 SIInstrInfo::moveScalarAddSub(SIInstrWorklist &Worklist, MachineInstr &Inst,  in moveScalarAddSub()
7419 void SIInstrInfo::lowerSelect(SIInstrWorklist &Worklist, MachineInstr &Inst,  in lowerSelect()
7502 void SIInstrInfo::lowerScalarAbs(SIInstrWorklist &Worklist,  in lowerScalarAbs()
7529 void SIInstrInfo::lowerScalarXnor(SIInstrWorklist &Worklist,  in lowerScalarXnor()
7594 void SIInstrInfo::splitScalarNotBinop(SIInstrWorklist &Worklist,  in splitScalarNotBinop()
7623 void SIInstrInfo::splitScalarBinOpN2(SIInstrWorklist &Worklist,  in splitScalarBinOpN2()
7652 void SIInstrInfo::splitScalar64BitUnaryOp(SIInstrWorklist &Worklist,  in splitScalar64BitUnaryOp()
7713 void SIInstrInfo::splitScalarSMulU64(SIInstrWorklist &Worklist,  in splitScalarSMulU64()
7822 void SIInstrInfo::splitScalarSMulPseudo(SIInstrWorklist &Worklist,  in splitScalarSMulPseudo()
7885 void SIInstrInfo::splitScalar64BitBinaryOp(SIInstrWorklist &Worklist,  in splitScalar64BitBinaryOp()
7952 void SIInstrInfo::splitScalar64BitXnor(SIInstrWorklist &Worklist,  in splitScalar64BitXnor()
7994 void SIInstrInfo::splitScalar64BitBCNT(SIInstrWorklist &Worklist,  in splitScalar64BitBCNT()
8032 void SIInstrInfo::splitScalar64BitBFE(SIInstrWorklist &Worklist,  in splitScalar64BitBFE()
8093 void SIInstrInfo::splitScalar64BitCountOp(SIInstrWorklist &Worklist,  in splitScalar64BitCountOp()
8148 void SIInstrInfo::addUsersToMoveToVALUWorklist(  in addUsersToMoveToVALUWorklist()
8184 void SIInstrInfo::movePackToVALU(SIInstrWorklist &Worklist,  in movePackToVALU()
8257 void SIInstrInfo::addSCCDefUsersToVALUWorklist(MachineOperand &Op,  in addSCCDefUsersToVALUWorklist()
8301 void SIInstrInfo::addSCCDefsToVALUWorklist(MachineInstr *SCCUseInst,  in addSCCDefsToVALUWorklist()
8319 const TargetRegisterClass *SIInstrInfo::getDestEquivalentVGPRClass(  in getDestEquivalentVGPRClass()
8369 Register SIInstrInfo::findUsedSGPR(const MachineInstr &MI,  in findUsedSGPR()
8439 MachineOperand *SIInstrInfo::getNamedOperand(MachineInstr &MI,  in getNamedOperand()
8448 uint64_t SIInstrInfo::getDefaultRsrcDataFormat() const {  in getDefaultRsrcDataFormat()
8473 uint64_t SIInstrInfo::getScratchRsrcWords23() const {  in getScratchRsrcWords23()
8497 bool SIInstrInfo::isLowLatencyInstruction(const MachineInstr &MI) const {  in isLowLatencyInstruction()
8503 bool SIInstrInfo::isHighLatencyDef(int Opc) const {  in isHighLatencyDef()
8508 unsigned SIInstrInfo::isStackAccess(const MachineInstr &MI,  in isStackAccess()
8521 unsigned SIInstrInfo::isSGPRStackAccess(const MachineInstr &MI,  in isSGPRStackAccess()
8529 unsigned SIInstrInfo::isLoadFromStackSlot(const MachineInstr &MI,  in isLoadFromStackSlot()
8543 unsigned SIInstrInfo::isStoreToStackSlot(const MachineInstr &MI,  in isStoreToStackSlot()
8557 unsigned SIInstrInfo::getInstBundleSize(const MachineInstr &MI) const {  in getInstBundleSize()
8569 unsigned SIInstrInfo::getInstSizeInBytes(const MachineInstr &MI) const {  in getInstSizeInBytes()
8630 bool SIInstrInfo::mayAccessFlatAddressSpace(const MachineInstr &MI) const {  in mayAccessFlatAddressSpace()
8644 bool SIInstrInfo::isNonUniformBranchInstr(MachineInstr &Branch) const {  in isNonUniformBranchInstr()
8648 void SIInstrInfo::convertNonUniformIfRegion(MachineBasicBlock *IfEntry,  in convertNonUniformIfRegion()
8673 void SIInstrInfo::convertNonUniformLoopRegion(  in convertNonUniformLoopRegion()
8718 SIInstrInfo::getSerializableTargetIndices() const {  in getSerializableTargetIndices()
8731 SIInstrInfo::CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II,  in CreateTargetPostRAHazardRecognizer()
8739 SIInstrInfo::CreateTargetPostRAHazardRecognizer(const MachineFunction &MF) const {  in CreateTargetPostRAHazardRecognizer()
8746 SIInstrInfo::CreateTargetMIHazardRecognizer(const InstrItineraryData *II,  in CreateTargetMIHazardRecognizer()
8758 SIInstrInfo::decomposeMachineOperandsTargetFlags(unsigned TF) const {  in decomposeMachineOperandsTargetFlags()
8763 SIInstrInfo::getSerializableDirectMachineOperandTargetFlags() const {  in getSerializableDirectMachineOperandTargetFlags()
8778 SIInstrInfo::getSerializableMachineMemOperandTargetFlags() const {  in getSerializableMachineMemOperandTargetFlags()
8788 unsigned SIInstrInfo::getLiveRangeSplitOpcode(Register SrcReg,  in getLiveRangeSplitOpcode()
8798 bool SIInstrInfo::isBasicBlockPrologue(const MachineInstr &MI,  in isBasicBlockPrologue()
8821 SIInstrInfo::getAddNoCarry(MachineBasicBlock &MBB,  in getAddNoCarry()
8836 MachineInstrBuilder SIInstrInfo::getAddNoCarry(MachineBasicBlock &MBB,  in getAddNoCarry()
8859 bool SIInstrInfo::isKillTerminator(unsigned Opcode) {  in isKillTerminator()
8869 const MCInstrDesc &SIInstrInfo::getKillTerminatorFromPseudo(unsigned Opcode) const {  in getKillTerminatorFromPseudo()
8880 bool SIInstrInfo::isLegalMUBUFImmOffset(unsigned Imm) const {  in isLegalMUBUFImmOffset()
8884 unsigned SIInstrInfo::getMaxMUBUFImmOffset(const GCNSubtarget &ST) {  in getMaxMUBUFImmOffset()
8891 void SIInstrInfo::fixImplicitOperands(MachineInstr &MI) const {  in fixImplicitOperands()
8904 bool SIInstrInfo::isBufferSMRD(const MachineInstr &MI) const {  in isBufferSMRD()
8924 bool SIInstrInfo::splitMUBUFOffset(uint32_t Imm, uint32_t &SOffset,  in splitMUBUFOffset()
8926   const uint32_t MaxOffset = SIInstrInfo::getMaxMUBUFImmOffset(ST);  in splitMUBUFOffset()
9000 bool SIInstrInfo::isLegalFLATOffset(int64_t Offset, unsigned AddrSpace,  in isLegalFLATOffset()
9024 SIInstrInfo::splitFlatOffset(int64_t COffsetVal, unsigned AddrSpace,  in splitFlatOffset()
9055 bool SIInstrInfo::allowNegativeFlatOffset(uint64_t FlatVariant) const {  in allowNegativeFlatOffset()
9083 bool SIInstrInfo::isAsmOnlyOpcode(int MCOp) const {  in isAsmOnlyOpcode()
9103 int SIInstrInfo::pseudoToMCOpcode(int Opcode) const {  in pseudoToMCOpcode()
9104   Opcode = SIInstrInfo::getNonSoftWaitcntOpcode(Opcode);  in pseudoToMCOpcode()
9336 MachineInstr *SIInstrInfo::createPHIDestinationCopy(  in createPHIDestinationCopy()
9351 MachineInstr *SIInstrInfo::createPHISourceCopy(  in createPHISourceCopy()
9371 bool llvm::SIInstrInfo::isWave32() const { return ST.isWave32(); }  in isWave32()
9373 MachineInstr *SIInstrInfo::foldMemoryOperandImpl(  in foldMemoryOperandImpl()
9410 unsigned SIInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,  in getInstrLatency()
9428 SIInstrInfo::getGenericInstructionUniformity(const MachineInstr &MI) const {  in getGenericInstructionUniformity()
9467   if (SIInstrInfo::isGenericAtomicRMWOpcode(opcode) ||  in getGenericInstructionUniformity()
9477 SIInstrInfo::getInstructionUniformity(const MachineInstr &MI) const {  in getInstructionUniformity()
9501     return SIInstrInfo::getGenericInstructionUniformity(MI);  in getInstructionUniformity()
9561 unsigned SIInstrInfo::getDSShaderTypeValue(const MachineFunction &MF) {  in getDSShaderTypeValue()
9583 bool SIInstrInfo::analyzeCompare(const MachineInstr &MI, Register &SrcReg,  in analyzeCompare()
9642 bool SIInstrInfo::optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg,  in optimizeCompareInstr()
9789 void SIInstrInfo::enforceOperandRCAlignment(MachineInstr &MI,  in enforceOperandRCAlignment()