Lines Matching refs:RI
68 RI(ST), ST(ST) { in SIInstrInfo()
204 RI.isSGPRClass(MRI.getRegClass(Op.getReg()))) { in isSafeToSink()
643 const SIRegisterInfo &RI = TII.getRegisterInfo(); in indirectCopyToAGPR() local
653 if (!Def->modifiesRegister(SrcReg, &RI)) in indirectCopyToAGPR()
668 if (I->modifiesRegister(DefOp.getReg(), &RI)) in indirectCopyToAGPR()
697 unsigned MaxVGPRs = RI.getRegPressureLimit(&AMDGPU::VGPR_32RegClass, in indirectCopyToAGPR()
714 if (!Tmp2 || RI.getHWRegIndex(Tmp2) >= MaxVGPRs) in indirectCopyToAGPR()
747 const SIRegisterInfo &RI = TII.getRegisterInfo(); in expandSGPRCopy() local
748 ArrayRef<int16_t> BaseIndices = RI.getRegSplitParts(RC, 4); in expandSGPRCopy()
754 Register DestSubReg = RI.getSubReg(DestReg, SubIdx); in expandSGPRCopy()
755 Register SrcSubReg = RI.getSubReg(SrcReg, SubIdx); in expandSGPRCopy()
764 unsigned Channel = RI.getChannelFromSubReg(SubIdx); in expandSGPRCopy()
765 SubIdx = RI.getSubRegFromChannel(Channel, 2); in expandSGPRCopy()
766 DestSubReg = RI.getSubReg(DestReg, SubIdx); in expandSGPRCopy()
767 SrcSubReg = RI.getSubReg(SrcReg, SubIdx); in expandSGPRCopy()
792 LastMI->addRegisterKilled(SrcReg, &RI); in expandSGPRCopy()
799 const TargetRegisterClass *RC = RI.getPhysRegBaseClass(DestReg); in copyPhysReg()
800 unsigned Size = RI.getRegSizeInBits(*RC); in copyPhysReg()
801 const TargetRegisterClass *SrcRC = RI.getPhysRegBaseClass(SrcReg); in copyPhysReg()
802 unsigned SrcSize = RI.getRegSizeInBits(*SrcRC); in copyPhysReg()
812 MCRegister SubReg = RI.getSubReg(RegToFix, AMDGPU::lo16); in copyPhysReg()
821 RC = RI.getPhysRegBaseClass(DestReg); in copyPhysReg()
822 Size = RI.getRegSizeInBits(*RC); in copyPhysReg()
823 SrcRC = RI.getPhysRegBaseClass(SrcReg); in copyPhysReg()
824 SrcSize = RI.getRegSizeInBits(*SrcRC); in copyPhysReg()
944 const bool Overlap = RI.regsOverlap(SrcReg, DestReg); in copyPhysReg()
958 bool DstLow = !AMDGPU::isHi(DestReg, RI); in copyPhysReg()
959 bool SrcLow = !AMDGPU::isHi(SrcReg, RI); in copyPhysReg()
960 MCRegister NewDestReg = RI.get32BitRegister(DestReg); in copyPhysReg()
961 MCRegister NewSrcReg = RI.get32BitRegister(SrcReg); in copyPhysReg()
1029 if (RC == RI.getVGPR64Class() && (SrcRC == RC || RI.isSGPRClass(SrcRC))) { in copyPhysReg()
1051 const bool Forward = RI.getHWRegIndex(DestReg) <= RI.getHWRegIndex(SrcReg); in copyPhysReg()
1052 if (RI.isSGPRClass(RC)) { in copyPhysReg()
1053 if (!RI.isSGPRClass(SrcRC)) { in copyPhysReg()
1057 const bool CanKillSuperReg = KillSrc && !RI.regsOverlap(SrcReg, DestReg); in copyPhysReg()
1065 if (RI.isAGPRClass(RC)) { in copyPhysReg()
1066 if (ST.hasGFX90AInsts() && RI.isAGPRClass(SrcRC)) in copyPhysReg()
1068 else if (RI.hasVGPRs(SrcRC) || in copyPhysReg()
1069 (ST.hasGFX90AInsts() && RI.isSGPRClass(SrcRC))) in copyPhysReg()
1073 } else if (RI.hasVGPRs(RC) && RI.isAGPRClass(SrcRC)) { in copyPhysReg()
1075 } else if ((Size % 64 == 0) && RI.hasVGPRs(RC) && in copyPhysReg()
1076 (RI.isProperlyAlignedRC(*RC) && in copyPhysReg()
1077 (SrcRC == RC || RI.isSGPRClass(SrcRC)))) { in copyPhysReg()
1097 ArrayRef<int16_t> SubIndices = RI.getRegSplitParts(RC, EltSize); in copyPhysReg()
1101 const bool Overlap = RI.regsOverlap(SrcReg, DestReg); in copyPhysReg()
1110 Register DestSubReg = RI.getSubReg(DestReg, SubIdx); in copyPhysReg()
1111 Register SrcSubReg = RI.getSubReg(SrcReg, SubIdx); in copyPhysReg()
1202 if (RI.isSGPRClass(RegClass)) { in materializeImmediate()
1203 if (RI.getRegSizeInBits(*RegClass) > 32) { in materializeImmediate()
1212 ArrayRef<int16_t> SubIndices = RI.getRegSplitParts(RegClass, EltSize); in materializeImmediate()
1217 get(Opcode), RI.getSubReg(DestReg, SubIndices[Idx])); in materializeImmediate()
1235 RI.getRegClass(AMDGPU::SReg_1_XEXECRegClassID); in insertVectorSelect()
1310 Register SReg2 = MRI.createVirtualRegister(RI.getBoolRC()); in insertVectorSelect()
1328 Register SReg2 = MRI.createVirtualRegister(RI.getBoolRC()); in insertVectorSelect()
1358 Register Reg = MRI.createVirtualRegister(RI.getBoolRC()); in insertEQ()
1371 Register Reg = MRI.createVirtualRegister(RI.getBoolRC()); in insertNE()
1381 if (RI.isAGPRClass(DstRC)) in getMovOpcode()
1383 if (RI.getRegSizeInBits(*DstRC) == 16) { in getMovOpcode()
1386 return RI.isSGPRClass(DstRC) ? AMDGPU::COPY : AMDGPU::V_MOV_B16_t16_e64; in getMovOpcode()
1387 } else if (RI.getRegSizeInBits(*DstRC) == 32) { in getMovOpcode()
1388 return RI.isSGPRClass(DstRC) ? AMDGPU::S_MOV_B32 : AMDGPU::V_MOV_B32_e32; in getMovOpcode()
1389 } else if (RI.getRegSizeInBits(*DstRC) == 64 && RI.isSGPRClass(DstRC)) { in getMovOpcode()
1391 } else if (RI.getRegSizeInBits(*DstRC) == 64 && !RI.isSGPRClass(DstRC)) { in getMovOpcode()
1735 if (RI.isSGPRClass(RC)) { in storeRegToStackSlot()
1757 if (RI.spillSGPRToVGPR()) in storeRegToStackSlot()
1763 SpillSize, RI, *MFI); in storeRegToStackSlot()
1962 if (RI.isSGPRClass(RC)) { in loadRegFromStackSlot()
1976 if (RI.spillSGPRToVGPR()) in loadRegFromStackSlot()
1987 SpillSize, RI, *MFI); in loadRegFromStackSlot()
2129 Register DstLo = RI.getSubReg(Dst, AMDGPU::sub0); in expandPostRAPseudo()
2130 Register DstHi = RI.getSubReg(Dst, AMDGPU::sub1); in expandPostRAPseudo()
2167 !RI.isAGPR(MBB.getParent()->getRegInfo(), SrcOp.getReg())) { in expandPostRAPseudo()
2180 .addReg(RI.getSubReg(SrcOp.getReg(), AMDGPU::sub0)) in expandPostRAPseudo()
2183 .addReg(RI.getSubReg(SrcOp.getReg(), AMDGPU::sub1)) in expandPostRAPseudo()
2204 Register DstLo = RI.getSubReg(Dst, AMDGPU::sub0); in expandPostRAPseudo()
2205 Register DstHi = RI.getSubReg(Dst, AMDGPU::sub1); in expandPostRAPseudo()
2284 if (RI.hasVGPRs(EltRC)) { in expandPostRAPseudo()
2287 Opc = RI.getRegSizeInBits(*EltRC) == 64 ? AMDGPU::S_MOVRELD_B64 in expandPostRAPseudo()
2299 .addReg(RI.getSubReg(VecReg, SubReg), RegState::Undef) in expandPostRAPseudo()
2337 .addReg(RI.getSubReg(VecReg, SubReg), RegState::Undef) in expandPostRAPseudo()
2381 .addReg(RI.getSubReg(VecReg, SubReg), RegState::Undef) in expandPostRAPseudo()
2394 Register RegLo = RI.getSubReg(Reg, AMDGPU::sub0); in expandPostRAPseudo()
2395 Register RegHi = RI.getSubReg(Reg, AMDGPU::sub1); in expandPostRAPseudo()
2497 Register DstHi = RI.getSubReg(Dst, AMDGPU::sub1); in expandPostRAPseudo()
2512 const TargetRegisterInfo &RI) const { in reMaterialize()
2545 unsigned Offset = RI.getSubRegIdxOffset(UseMO->getSubReg()); in reMaterialize()
2546 unsigned SubregSize = RI.getSubRegIdxSize(UseMO->getSubReg()); in reMaterialize()
2562 RI.getAllocatableClass(getRegClass(TID, 0, &RI, *MF)); in reMaterialize()
2592 TargetInstrInfo::reMaterialize(MBB, I, DestReg, SubIdx, Orig, RI); in reMaterialize()
2617 MovDPP.addDef(RI.getSubReg(Dst, Sub)); in expandMovDPP64()
2635 MovDPP.addReg(RI.getSubReg(Src, Sub)); in expandMovDPP64()
3187 return RI.hasVGPRs(RC) && NumInsts <= 6; in canInsertSelect()
3205 return RI.isSGPRClass(RC); in canInsertSelect()
3224 unsigned DstSize = RI.getRegSizeInBits(*DstRC); in insertSelect()
3408 bool isVGPRCopy = RI.isVGPR(*MRI, DstReg); in FoldImmediate()
3415 if (RI.isAGPR(*MRI, DstReg)) { in FoldImmediate()
3430 DstReg = RI.get32BitRegister(DstReg); in FoldImmediate()
3438 !RI.getRegClass(NewMCID.operands()[0].RegClass)->contains(DstReg)) in FoldImmediate()
3482 if (RI.isSGPRClass(MRI->getRegClass(RegSrc->getReg())) && in FoldImmediate()
3486 if (!Src2->isReg() || RI.isSGPRClass(MRI->getRegClass(Src2->getReg()))) in FoldImmediate()
3562 RI.isSGPRReg(*MRI, Src0->getReg())) { in FoldImmediate()
3575 else if (RI.isSGPRReg(*MRI, Src1->getReg())) in FoldImmediate()
3653 Dummy0, &RI) || in checkInstOffsetsDoNotOverlap()
3655 Dummy1, &RI)) in checkInstOffsetsDoNotOverlap()
3874 !RI.isSGPRReg(MBB.getParent()->getRegInfo(), Src0->getReg()))) { in convertToThreeAddress()
4025 return MI.modifiesRegister(AMDGPU::EXEC, &RI) || in isSchedulingBoundary()
4093 if (!RI.isSGPRReg(MRI, MI.getOperand(0).getReg())) in mayReadEXEC()
4097 return MI.readsRegister(AMDGPU::EXEC, &RI); in mayReadEXEC()
4108 return !isSALU(MI) || MI.readsRegister(AMDGPU::EXEC, &RI); in mayReadEXEC()
4260 return RI.opCanUseInlineConstant(OpInfo.OperandType); in isImmOperandLegal()
4263 if (!RI.opCanUseLiteralConstant(OpInfo.OperandType)) in isImmOperandLegal()
4315 if (!Src1->isReg() || !RI.isVGPR(MRI, Src1->getReg())) in canShrink()
4328 if (!Src2->isReg() || !RI.isVGPR(MRI, Src2->getReg()) || in canShrink()
4339 if (Src1 && (!Src1->isReg() || !RI.isVGPR(MRI, Src1->getReg()) || in canShrink()
4429 return RI.isSGPRClass(MRI.getRegClass(MO.getReg())); in usesConstantBus()
4533 const TargetRegisterClass *RC = MI.getRegClassConstraint(I, this, &RI); in verifyInstruction()
4627 const TargetRegisterClass *RC = RI.getRegClassForReg(MRI, Reg); in verifyInstruction()
4628 if (RI.hasVectorRegisters(RC) && MO.getSubReg()) { in verifyInstruction()
4630 RI.getSubRegisterClass(RC, MO.getSubReg()); in verifyInstruction()
4631 RC = RI.getCompatibleSubRegClass(RC, SubRC, MO.getSubReg()); in verifyInstruction()
4637 if (!RC || !RI.isProperlyAlignedRC(*RC)) { in verifyInstruction()
4647 const TargetRegisterClass *RC = RI.getRegClass(RegClass); in verifyInstruction()
4671 if (!MO.isReg() || !RI.hasVGPRs(RI.getRegClassForReg(MRI, MO.getReg()))) { in verifyInstruction()
4770 uint32_t DstSize = RI.getRegSizeInBits(*DstRC) / 32; in verifyInstruction()
4828 return !RI.regsOverlap(SGPRUsed, SGPR); in verifyInstruction()
4973 !isSubRegOf(RI, ImpUse, IsDst ? *Dst : Src0)) { in verifyInstruction()
5135 (RI.isAGPR(MRI, Dst->getReg()) != RI.isAGPR(MRI, Data->getReg()))) { in verifyInstruction()
5141 (RI.isAGPR(MRI, Data->getReg()) != RI.isAGPR(MRI, Data2->getReg()))) { in verifyInstruction()
5147 if ((Dst && RI.isAGPR(MRI, Dst->getReg())) || in verifyInstruction()
5148 (Data && RI.isAGPR(MRI, Data->getReg())) || in verifyInstruction()
5149 (Data2 && RI.isAGPR(MRI, Data2->getReg()))) { in verifyInstruction()
5164 return !(RI.getHWRegIndex(Reg) & 1); in verifyInstruction()
5166 return RI.getRegSizeInBits(RC) > 32 && RI.isProperlyAlignedRC(RC) && in verifyInstruction()
5167 !(RI.getChannelFromSubReg(Op->getSubReg()) & 1); in verifyInstruction()
5193 if (Src->isReg() && RI.isSGPRReg(MRI, Src->getReg())) { in verifyInstruction()
5228 RI.isAGPR(MRI, MI.getOperand(0).getReg()) ? in getVALUOp()
5421 adjustAllocatableRegClass(const GCNSubtarget &ST, const SIRegisterInfo &RI, in adjustAllocatableRegClass() argument
5453 return RI.getProperlyAlignedRC(RI.getRegClass(RCID)); in adjustAllocatableRegClass()
5482 return adjustAllocatableRegClass(ST, RI, MF.getRegInfo(), TID, RegClass, in getRegClass()
5496 return RI.getPhysRegBaseClass(Reg); in getOpRegClass()
5500 return adjustAllocatableRegClass(ST, RI, MRI, Desc, RCID, true); in getOpRegClass()
5509 const TargetRegisterClass *RC = RI.getRegClass(RCID); in legalizeOpWithMove()
5510 unsigned Size = RI.getRegSizeInBits(*RC); in legalizeOpWithMove()
5514 else if (RI.isSGPRClass(RC)) in legalizeOpWithMove()
5517 const TargetRegisterClass *VRC = RI.getEquivalentVGPRClass(RC); in legalizeOpWithMove()
5587 const TargetRegisterClass *DRC = RI.getRegClass(OpInfo.RegClass); in isLegalRegOperand()
5595 const TargetRegisterClass *SuperRC = RI.getLargestLegalSuperClass(RC, *MF); in isLegalRegOperand()
5599 DRC = RI.getMatchingSuperRegClass(SuperRC, DRC, MO.getSubReg()); in isLegalRegOperand()
5624 OpInfo.RegClass != -1 ? RI.getRegClass(OpInfo.RegClass) : nullptr; in isOperandLegal()
5666 bool IsAGPR = RI.isAGPR(MRI, MO->getReg()); in isOperandLegal()
5680 RI.isAGPR(MRI, MI.getOperand(DataIdx).getReg()) != IsAGPR) in isOperandLegal()
5684 RI.isAGPR(MRI, MI.getOperand(VDstIdx).getReg()) != IsAGPR) in isOperandLegal()
5690 RI.isAGPR(MRI, MI.getOperand(Data1Idx).getReg()) != IsAGPR) in isOperandLegal()
5695 RI.isSGPRReg(MRI, MO->getReg())) in isOperandLegal()
5747 RI.isSGPRReg(MRI, Src0.getReg())) in legalizeOperandsVOP2()
5755 if (Src0.isReg() && RI.isVGPR(MRI, Src0.getReg())) { in legalizeOperandsVOP2()
5761 if (Src1.isReg() && RI.isVGPR(MRI, Src1.getReg())) { in legalizeOperandsVOP2()
5772 if (Src0.isReg() && RI.isAGPR(MRI, Src0.getReg())) in legalizeOperandsVOP2()
5775 if (Src1.isReg() && RI.isAGPR(MRI, Src1.getReg())) in legalizeOperandsVOP2()
5781 if (!RI.isVGPR(MRI, MI.getOperand(Src2Idx).getReg())) in legalizeOperandsVOP2()
5794 RI.isVGPR(MRI, Src1.getReg())) { in legalizeOperandsVOP2()
5866 if (Src1.isReg() && !RI.isSGPRClass(MRI.getRegClass(Src1.getReg()))) { in legalizeOperandsVOP3()
5872 if (Src2.isReg() && !RI.isSGPRClass(MRI.getRegClass(Src2.getReg()))) { in legalizeOperandsVOP3()
5911 if (RI.hasAGPRs(RI.getRegClassForReg(MRI, MO.getReg())) && in legalizeOperandsVOP3()
5917 if (!RI.isSGPRClass(RI.getRegClassForReg(MRI, MO.getReg()))) in legalizeOperandsVOP3()
5937 !RI.isVGPR(MRI, MI.getOperand(VOP3Idx[2]).getReg())) in legalizeOperandsVOP3()
5944 const TargetRegisterClass *SRC = RI.getEquivalentSGPRClass(VRC); in readlaneVGPRToSGPR()
5946 unsigned SubRegs = RI.getRegSizeInBits(*VRC) / 32; in readlaneVGPRToSGPR()
5948 if (RI.hasAGPRs(VRC)) { in readlaneVGPRToSGPR()
5949 VRC = RI.getEquivalentVGPRClass(VRC); in readlaneVGPRToSGPR()
5969 .addReg(SrcReg, 0, RI.getSubRegFromChannel(i)); in readlaneVGPRToSGPR()
5978 MIB.addImm(RI.getSubRegFromChannel(i)); in readlaneVGPRToSGPR()
5991 if (SBase && !RI.isSGPRClass(MRI.getRegClass(SBase->getReg()))) { in legalizeOperandsSMRD()
5996 if (SOff && !RI.isSGPRClass(MRI.getRegClass(SOff->getReg()))) { in legalizeOperandsSMRD()
6018 if (RI.isSGPRReg(MRI, SAddr.getReg())) in moveFlatAddrToVGPR()
6091 if (!SAddr || RI.isSGPRClass(MRI.getRegClass(SAddr->getReg()))) in legalizeOperandsFLAT()
6110 const TargetRegisterClass *OpRC = RI.getSubClassWithSubReg( in legalizeGenericOperand()
6111 RI.getRegClassForReg(MRI, OpReg), OpSubReg); in legalizeGenericOperand()
6138 if (!RI.isSGPRClass(DstRC) && !Copy->readsRegister(AMDGPU::EXEC, &RI) && in legalizeGenericOperand()
6473 if (RI.hasVectorRegisters(OpRC)) { in legalizeOperands()
6483 if (VRC || !RI.isSGPRClass(getOpRegClass(MI, 0))) { in legalizeOperands()
6489 VRC = RI.isAGPRClass(getOpRegClass(MI, 0)) in legalizeOperands()
6490 ? RI.getEquivalentAGPRClass(SRC) in legalizeOperands()
6491 : RI.getEquivalentVGPRClass(SRC); in legalizeOperands()
6493 VRC = RI.isAGPRClass(getOpRegClass(MI, 0)) in legalizeOperands()
6494 ? RI.getEquivalentAGPRClass(VRC) in legalizeOperands()
6495 : RI.getEquivalentVGPRClass(VRC); in legalizeOperands()
6524 if (RI.hasVGPRs(DstRC)) { in legalizeOperands()
6534 const TargetRegisterClass *VRC = RI.getEquivalentVGPRClass(OpRC); in legalizeOperands()
6564 if (Src.isReg() && RI.hasVectorRegisters(MRI.getRegClass(Src.getReg()))) in legalizeOperands()
6576 if (Src.isReg() && RI.hasVectorRegisters(MRI.getRegClass(Src.getReg()))) in legalizeOperands()
6591 if (SRsrc && !RI.isSGPRClass(MRI.getRegClass(SRsrc->getReg()))) in legalizeOperands()
6596 if (SSamp && !RI.isSGPRClass(MRI.getRegClass(SSamp->getReg()))) in legalizeOperands()
6605 if (!RI.isSGPRClass(MRI.getRegClass(Dest->getReg()))) { in legalizeOperands()
6650 !RI.isSGPRClass(MRI.getRegClass(Soffset->getReg()))) { in legalizeOperands()
6660 if (Rsrc->isReg() && !RI.isSGPRClass(MRI.getRegClass(Rsrc->getReg()))) { in legalizeOperands()
6694 const auto *BoolXExecRC = RI.getRegClass(AMDGPU::SReg_1_XEXECRegClassID); in legalizeOperands()
7017 Register VCC = RI.getVCC(); in moveToVALUImpl()
7072 const auto *CarryRC = RI.getRegClass(AMDGPU::SReg_1_XEXECRegClassID); in moveToVALUImpl()
7083 Register DestReg = MRI.createVirtualRegister(RI.getEquivalentVGPRClass( in moveToVALUImpl()
7110 RI.getEquivalentVGPRClass(MRI.getRegClass(Dest0.getReg())); in moveToVALUImpl()
7173 Register CondReg = MRI.createVirtualRegister(RI.getWaveMaskRegClass()); in moveToVALUImpl()
7252 RI.isVGPR(MRI, Inst.getOperand(1).getReg())) { in moveToVALUImpl()
7262 NewDstRC == RI.getRegClassForReg(MRI, Inst.getOperand(1).getReg())) { in moveToVALUImpl()
7300 Src.isReg() && RI.isVGPR(MRI, Src.getReg())) in moveToVALUImpl()
7448 RI.getRegClass(AMDGPU::SReg_1_XEXECRegClassID); in lowerSelect()
7457 if (CandI.findRegisterDefOperandIdx(AMDGPU::SCC, false, false, &RI) != in lowerSelect()
7481 RI.getEquivalentVGPRClass(MRI.getRegClass(Dest.getReg()))); in lowerSelect()
7557 RI.isSGPRClass(MRI.getRegClass(Src0.getReg())); in lowerScalarXnor()
7559 RI.isSGPRClass(MRI.getRegClass(Src1.getReg())); in lowerScalarXnor()
7670 RI.getSubRegisterClass(Src0RC, AMDGPU::sub0); in splitScalar64BitUnaryOp()
7676 const TargetRegisterClass *NewDestRC = RI.getEquivalentVGPRClass(DestRC); in splitScalar64BitUnaryOp()
7678 RI.getSubRegisterClass(NewDestRC, AMDGPU::sub0); in splitScalar64BitUnaryOp()
7732 RI.getSubRegisterClass(Src0RC, AMDGPU::sub0); in splitScalarSMulU64()
7733 if (RI.isSGPRClass(Src0SubRC)) in splitScalarSMulU64()
7734 Src0SubRC = RI.getEquivalentVGPRClass(Src0SubRC); in splitScalarSMulU64()
7736 RI.getSubRegisterClass(Src1RC, AMDGPU::sub0); in splitScalarSMulU64()
7737 if (RI.isSGPRClass(Src1SubRC)) in splitScalarSMulU64()
7738 Src1SubRC = RI.getEquivalentVGPRClass(Src1SubRC); in splitScalarSMulU64()
7841 RI.getSubRegisterClass(Src0RC, AMDGPU::sub0); in splitScalarSMulPseudo()
7842 if (RI.isSGPRClass(Src0SubRC)) in splitScalarSMulPseudo()
7843 Src0SubRC = RI.getEquivalentVGPRClass(Src0SubRC); in splitScalarSMulPseudo()
7845 RI.getSubRegisterClass(Src1RC, AMDGPU::sub0); in splitScalarSMulPseudo()
7846 if (RI.isSGPRClass(Src1SubRC)) in splitScalarSMulPseudo()
7847 Src1SubRC = RI.getEquivalentVGPRClass(Src1SubRC); in splitScalarSMulPseudo()
7904 RI.getSubRegisterClass(Src0RC, AMDGPU::sub0); in splitScalar64BitBinaryOp()
7910 RI.getSubRegisterClass(Src1RC, AMDGPU::sub0); in splitScalar64BitBinaryOp()
7922 const TargetRegisterClass *NewDestRC = RI.getEquivalentVGPRClass(DestRC); in splitScalar64BitBinaryOp()
7924 RI.getSubRegisterClass(NewDestRC, AMDGPU::sub0); in splitScalar64BitBinaryOp()
7972 if (Src0.isReg() && RI.isSGPRReg(MRI, Src0.getReg())) { in splitScalar64BitXnor()
8014 RI.getSubRegisterClass(SrcRC, AMDGPU::sub0); in splitScalar64BitBCNT()
8118 RI.getSubRegisterClass(SrcRC, AMDGPU::sub0); in splitScalar64BitCountOp()
8172 if (!RI.hasVectorRegisters(getOpRegClass(UseMI, OpNo))) { in addUsersToMoveToVALUWorklist()
8272 int SCCIdx = MI.findRegisterUseOperandIdx(AMDGPU::SCC, false, &RI); in addSCCDefUsersToVALUWorklist()
8289 if (MI.findRegisterDefOperandIdx(AMDGPU::SCC, false, false, &RI) != -1) in addSCCDefUsersToVALUWorklist()
8310 if (MI.modifiesRegister(AMDGPU::VCC, &RI)) in addSCCDefsToVALUWorklist()
8312 if (MI.definesRegister(AMDGPU::SCC, &RI)) { in addSCCDefsToVALUWorklist()
8336 if (RI.isAGPRClass(SrcRC)) { in getDestEquivalentVGPRClass()
8337 if (RI.isAGPRClass(NewDstRC)) in getDestEquivalentVGPRClass()
8344 NewDstRC = RI.getEquivalentAGPRClass(NewDstRC); in getDestEquivalentVGPRClass()
8347 NewDstRC = RI.getEquivalentVGPRClass(NewDstRC); in getDestEquivalentVGPRClass()
8353 if (RI.isVGPRClass(NewDstRC) || NewDstRC == &AMDGPU::VReg_1RegClass) in getDestEquivalentVGPRClass()
8356 NewDstRC = RI.getEquivalentVGPRClass(NewDstRC); in getDestEquivalentVGPRClass()
8401 RI.getRegClass(Desc.operands()[Idx].RegClass); in findUsedSGPR()
8402 bool IsRequiredSGPR = RI.isSGPRClass(OpRC); in findUsedSGPR()
8409 if (RI.isSGPRClass(RegRC)) in findUsedSGPR()
8658 Register DstReg = MRI.createVirtualRegister(RI.getBoolRC()); in convertNonUniformIfRegion()
8685 Register DstReg = MRI.createVirtualRegister(RI.getBoolRC()); in convertNonUniformLoopRegion()
8686 Register BackEdgeReg = MRI.createVirtualRegister(RI.getBoolRC()); in convertNonUniformLoopRegion()
8693 Register ZeroReg = MRI.createVirtualRegister(RI.getBoolRC()); in convertNonUniformLoopRegion()
8809 IsNullOrVectorRegister = !RI.isSGPRClass(RI.getRegClassForReg(MRI, Reg)); in isBasicBlockPrologue()
8817 MI.modifiesRegister(AMDGPU::EXEC, &RI))); in isBasicBlockPrologue()
8829 Register UnusedCarry = MRI.createVirtualRegister(RI.getBoolRC()); in getAddNoCarry()
8830 MRI.setRegAllocationHint(UnusedCarry, 0, RI.getVCC()); in getAddNoCarry()
8846 ? Register(RI.getVCC()) in getAddNoCarry()
8848 *RI.getBoolRC(), I, /* RestoreAfter */ false, in getAddNoCarry()
8914 return RI.getRegClass(RCID)->hasSubClassEq(&AMDGPU::SGPR_128RegClass); in isBufferSMRD()
9492 RI.getPhysRegBaseClass(srcOp.getReg()); in getInstructionUniformity()
9493 return RI.isSGPRClass(regClass) ? InstructionUniformity::AlwaysUniform in getInstructionUniformity()
9546 const RegisterBank *RegBank = RBI->getRegBank(Reg, MRI, RI); in getInstructionUniformity()
9725 if (I->modifiesRegister(AMDGPU::SCC, &RI) || in optimizeCompareInstr()
9726 I->killsRegister(AMDGPU::SCC, &RI)) in optimizeCompareInstr()
9806 bool IsAGPR = RI.isAGPR(MRI, DataReg); in enforceOperandRCAlignment()