Lines Matching refs:LoopBB
6148 MachineBasicBlock &LoopBB, MachineBasicBlock &BodyBB, const DebugLoc &DL, in emitLoadScalarOpsFromVGPRLoop() argument
6162 MachineBasicBlock::iterator I = LoopBB.begin(); in emitLoadScalarOpsFromVGPRLoop()
6175 BuildMI(LoopBB, I, DL, TII.get(AMDGPU::V_READFIRSTLANE_B32), CurReg) in emitLoadScalarOpsFromVGPRLoop()
6180 BuildMI(LoopBB, I, DL, TII.get(AMDGPU::V_CMP_EQ_U32_e64), NewCondReg) in emitLoadScalarOpsFromVGPRLoop()
6189 BuildMI(LoopBB, I, DL, TII.get(AndOpc), AndReg) in emitLoadScalarOpsFromVGPRLoop()
6208 BuildMI(LoopBB, I, DL, TII.get(AMDGPU::V_READFIRSTLANE_B32), CurRegLo) in emitLoadScalarOpsFromVGPRLoop()
6212 BuildMI(LoopBB, I, DL, TII.get(AMDGPU::V_READFIRSTLANE_B32), CurRegHi) in emitLoadScalarOpsFromVGPRLoop()
6221 BuildMI(LoopBB, I, DL, TII.get(AMDGPU::REG_SEQUENCE), CurReg) in emitLoadScalarOpsFromVGPRLoop()
6228 auto Cmp = BuildMI(LoopBB, I, DL, TII.get(AMDGPU::V_CMP_EQ_U64_e64), in emitLoadScalarOpsFromVGPRLoop()
6242 BuildMI(LoopBB, I, DL, TII.get(AndOpc), AndReg) in emitLoadScalarOpsFromVGPRLoop()
6255 BuildMI(LoopBB, I, DL, TII.get(AMDGPU::REG_SEQUENCE), SScalarOp); in emitLoadScalarOpsFromVGPRLoop()
6271 BuildMI(LoopBB, I, DL, TII.get(SaveExecOpc), SaveExec) in emitLoadScalarOpsFromVGPRLoop()
6282 BuildMI(BodyBB, I, DL, TII.get(AMDGPU::SI_WATERFALL_LOOP)).addMBB(&LoopBB); in emitLoadScalarOpsFromVGPRLoop()
6337 MachineBasicBlock *LoopBB = MF.CreateMachineBasicBlock(); in loadMBUFScalarOperandsFromVGPR() local
6343 MF.insert(MBBI, LoopBB); in loadMBUFScalarOperandsFromVGPR()
6347 LoopBB->addSuccessor(BodyBB); in loadMBUFScalarOperandsFromVGPR()
6348 BodyBB->addSuccessor(LoopBB); in loadMBUFScalarOperandsFromVGPR()
6357 MBB.addSuccessor(LoopBB); in loadMBUFScalarOperandsFromVGPR()
6364 MDT->addNewBlock(LoopBB, &MBB); in loadMBUFScalarOperandsFromVGPR()
6365 MDT->addNewBlock(BodyBB, LoopBB); in loadMBUFScalarOperandsFromVGPR()
6374 emitLoadScalarOpsFromVGPRLoop(TII, MRI, MBB, *LoopBB, *BodyBB, DL, ScalarOps); in loadMBUFScalarOperandsFromVGPR()