7686   Register DestSub1 = MRI.createVirtualRegister(NewDestSubRC);  in splitScalar64BitUnaryOp()  local
7687   MachineInstr &HiHalf = *BuildMI(MBB, MII, DL, InstDesc, DestSub1).add(SrcReg0Sub1);  in splitScalar64BitUnaryOp()
7690     std::swap(DestSub0, DestSub1);  in splitScalar64BitUnaryOp()
7696     .addReg(DestSub1)  in splitScalar64BitUnaryOp()
7721   Register DestSub1 = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);  in splitScalarSMulU64()  local
7795       BuildMI(MBB, MII, DL, get(AMDGPU::V_ADD_U32_e32), DestSub1)  in splitScalarSMulU64()
7802       .addReg(DestSub1)  in splitScalarSMulU64()
7830   Register DestSub1 = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);  in splitScalarSMulPseudo()  local
7861       BuildMI(MBB, MII, DL, get(NewOpc), DestSub1).add(Op1L).add(Op0L);  in splitScalarSMulPseudo()
7871       .addReg(DestSub1)  in splitScalarSMulPseudo()
7931   Register DestSub1 = MRI.createVirtualRegister(NewDestSubRC);  in splitScalar64BitBinaryOp()  local
7932   MachineInstr &HiHalf = *BuildMI(MBB, MII, DL, InstDesc, DestSub1)  in splitScalar64BitBinaryOp()
7940     .addReg(DestSub1)  in splitScalar64BitBinaryOp()