Lines Matching refs:DestSub0
7680 Register DestSub0 = MRI.createVirtualRegister(NewDestSubRC); in splitScalar64BitUnaryOp() local
7681 MachineInstr &LoHalf = *BuildMI(MBB, MII, DL, InstDesc, DestSub0).add(SrcReg0Sub0); in splitScalar64BitUnaryOp()
7690 std::swap(DestSub0, DestSub1); in splitScalar64BitUnaryOp()
7694 .addReg(DestSub0) in splitScalar64BitUnaryOp()
7720 Register DestSub0 = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass); in splitScalarSMulU64() local
7785 BuildMI(MBB, MII, DL, get(AMDGPU::V_MUL_LO_U32_e64), DestSub0) in splitScalarSMulU64()
7800 .addReg(DestSub0) in splitScalarSMulU64()
7829 Register DestSub0 = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass); in splitScalarSMulPseudo() local
7864 BuildMI(MBB, MII, DL, get(AMDGPU::V_MUL_LO_U32_e64), DestSub0) in splitScalarSMulPseudo()
7869 .addReg(DestSub0) in splitScalarSMulPseudo()
7926 Register DestSub0 = MRI.createVirtualRegister(NewDestSubRC); in splitScalar64BitBinaryOp() local
7927 MachineInstr &LoHalf = *BuildMI(MBB, MII, DL, InstDesc, DestSub0) in splitScalar64BitBinaryOp()
7938 .addReg(DestSub0) in splitScalar64BitBinaryOp()