3091 static void preserveCondRegFlags(MachineOperand &CondReg,  in preserveCondRegFlags()  argument
3093   CondReg.setIsUndef(OrigCond.isUndef());  in preserveCondRegFlags()
3094   CondReg.setIsKill(OrigCond.isKill());  in preserveCondRegFlags()
3146   MachineOperand &CondReg = CondBr->getOperand(1);  in insertBranch()  local
3147   CondReg.setIsUndef(Cond[1].isUndef());  in insertBranch()
3148   CondReg.setIsKill(Cond[1].isKill());  in insertBranch()
6165   Register CondReg;  in emitLoadScalarOpsFromVGPRLoop()  local
6185       if (!CondReg) // First.  in emitLoadScalarOpsFromVGPRLoop()
6186         CondReg = NewCondReg;  in emitLoadScalarOpsFromVGPRLoop()
6190             .addReg(CondReg)  in emitLoadScalarOpsFromVGPRLoop()
6192         CondReg = AndReg;  in emitLoadScalarOpsFromVGPRLoop()
6238         if (!CondReg) // First.  in emitLoadScalarOpsFromVGPRLoop()
6239           CondReg = NewCondReg;  in emitLoadScalarOpsFromVGPRLoop()
6243               .addReg(CondReg)  in emitLoadScalarOpsFromVGPRLoop()
6245           CondReg = AndReg;  in emitLoadScalarOpsFromVGPRLoop()
6268   MRI.setSimpleHint(SaveExec, CondReg);  in emitLoadScalarOpsFromVGPRLoop()
6272       .addReg(CondReg, RegState::Kill);  in emitLoadScalarOpsFromVGPRLoop()
7015     Register CondReg = Inst.getOperand(1).getReg();  in moveToVALUImpl()  local
7016     bool IsSCC = CondReg == AMDGPU::SCC;  in moveToVALUImpl()
7022         .addReg(IsSCC ? VCC : CondReg);  in moveToVALUImpl()
7173     Register CondReg = MRI.createVirtualRegister(RI.getWaveMaskRegClass());  in moveToVALUImpl()  local
7175         BuildMI(*MBB, Inst, Inst.getDebugLoc(), get(NewOpcode), CondReg)  in moveToVALUImpl()
7193     addSCCDefUsersToVALUWorklist(SCCOp, Inst, Worklist, CondReg);  in moveToVALUImpl()
7432   Register CondReg = Cond.getReg();  in lowerSelect()  local
7433   bool IsSCC = (CondReg == AMDGPU::SCC);  in lowerSelect()
7441     MRI.replaceRegWith(Dest.getReg(), CondReg);  in lowerSelect()
7445   Register NewCondReg = CondReg;  in lowerSelect()