88   addRegisterClass(MVT::i1, &AMDGPU::VReg_1RegClass);  in SITargetLowering()
89   addRegisterClass(MVT::i64, &AMDGPU::SReg_64RegClass);  in SITargetLowering()
91   addRegisterClass(MVT::i32, &AMDGPU::SReg_32RegClass);  in SITargetLowering()
92   addRegisterClass(MVT::f32, &AMDGPU::VGPR_32RegClass);  in SITargetLowering()
94   addRegisterClass(MVT::v2i32, &AMDGPU::SReg_64RegClass);  in SITargetLowering()
99   addRegisterClass(MVT::f64, V64RegClass);  in SITargetLowering()
100   addRegisterClass(MVT::v2f32, V64RegClass);  in SITargetLowering()
102   addRegisterClass(MVT::v3i32, &AMDGPU::SGPR_96RegClass);  in SITargetLowering()
103   addRegisterClass(MVT::v3f32, TRI->getVGPRClassForBitWidth(96));  in SITargetLowering()
105   addRegisterClass(MVT::v2i64, &AMDGPU::SGPR_128RegClass);  in SITargetLowering()
106   addRegisterClass(MVT::v2f64, &AMDGPU::SGPR_128RegClass);  in SITargetLowering()
108   addRegisterClass(MVT::v4i32, &AMDGPU::SGPR_128RegClass);  in SITargetLowering()
109   addRegisterClass(MVT::v4f32, TRI->getVGPRClassForBitWidth(128));  in SITargetLowering()
111   addRegisterClass(MVT::v5i32, &AMDGPU::SGPR_160RegClass);  in SITargetLowering()
112   addRegisterClass(MVT::v5f32, TRI->getVGPRClassForBitWidth(160));  in SITargetLowering()
114   addRegisterClass(MVT::v6i32, &AMDGPU::SGPR_192RegClass);  in SITargetLowering()
115   addRegisterClass(MVT::v6f32, TRI->getVGPRClassForBitWidth(192));  in SITargetLowering()
117   addRegisterClass(MVT::v3i64, &AMDGPU::SGPR_192RegClass);  in SITargetLowering()
118   addRegisterClass(MVT::v3f64, TRI->getVGPRClassForBitWidth(192));  in SITargetLowering()
120   addRegisterClass(MVT::v7i32, &AMDGPU::SGPR_224RegClass);  in SITargetLowering()
121   addRegisterClass(MVT::v7f32, TRI->getVGPRClassForBitWidth(224));  in SITargetLowering()
123   addRegisterClass(MVT::v8i32, &AMDGPU::SGPR_256RegClass);  in SITargetLowering()
124   addRegisterClass(MVT::v8f32, TRI->getVGPRClassForBitWidth(256));  in SITargetLowering()
126   addRegisterClass(MVT::v4i64, &AMDGPU::SGPR_256RegClass);  in SITargetLowering()
127   addRegisterClass(MVT::v4f64, TRI->getVGPRClassForBitWidth(256));  in SITargetLowering()
129   addRegisterClass(MVT::v9i32, &AMDGPU::SGPR_288RegClass);  in SITargetLowering()
130   addRegisterClass(MVT::v9f32, TRI->getVGPRClassForBitWidth(288));  in SITargetLowering()
132   addRegisterClass(MVT::v10i32, &AMDGPU::SGPR_320RegClass);  in SITargetLowering()
133   addRegisterClass(MVT::v10f32, TRI->getVGPRClassForBitWidth(320));  in SITargetLowering()
135   addRegisterClass(MVT::v11i32, &AMDGPU::SGPR_352RegClass);  in SITargetLowering()
136   addRegisterClass(MVT::v11f32, TRI->getVGPRClassForBitWidth(352));  in SITargetLowering()
138   addRegisterClass(MVT::v12i32, &AMDGPU::SGPR_384RegClass);  in SITargetLowering()
139   addRegisterClass(MVT::v12f32, TRI->getVGPRClassForBitWidth(384));  in SITargetLowering()
141   addRegisterClass(MVT::v16i32, &AMDGPU::SGPR_512RegClass);  in SITargetLowering()
142   addRegisterClass(MVT::v16f32, TRI->getVGPRClassForBitWidth(512));  in SITargetLowering()
144   addRegisterClass(MVT::v8i64, &AMDGPU::SGPR_512RegClass);  in SITargetLowering()
145   addRegisterClass(MVT::v8f64, TRI->getVGPRClassForBitWidth(512));  in SITargetLowering()
147   addRegisterClass(MVT::v16i64, &AMDGPU::SGPR_1024RegClass);  in SITargetLowering()
148   addRegisterClass(MVT::v16f64, TRI->getVGPRClassForBitWidth(1024));  in SITargetLowering()
152       addRegisterClass(MVT::i16, &AMDGPU::VGPR_16RegClass);  in SITargetLowering()
153       addRegisterClass(MVT::f16, &AMDGPU::VGPR_16RegClass);  in SITargetLowering()
154       addRegisterClass(MVT::bf16, &AMDGPU::VGPR_16RegClass);  in SITargetLowering()
156       addRegisterClass(MVT::i16, &AMDGPU::SReg_32RegClass);  in SITargetLowering()
157       addRegisterClass(MVT::f16, &AMDGPU::SReg_32RegClass);  in SITargetLowering()
158       addRegisterClass(MVT::bf16, &AMDGPU::SReg_32RegClass);  in SITargetLowering()
162     addRegisterClass(MVT::v2i16, &AMDGPU::SReg_32RegClass);  in SITargetLowering()
163     addRegisterClass(MVT::v2f16, &AMDGPU::SReg_32RegClass);  in SITargetLowering()
164     addRegisterClass(MVT::v2bf16, &AMDGPU::SReg_32RegClass);  in SITargetLowering()
165     addRegisterClass(MVT::v4i16, &AMDGPU::SReg_64RegClass);  in SITargetLowering()
166     addRegisterClass(MVT::v4f16, &AMDGPU::SReg_64RegClass);  in SITargetLowering()
167     addRegisterClass(MVT::v4bf16, &AMDGPU::SReg_64RegClass);  in SITargetLowering()
168     addRegisterClass(MVT::v8i16, &AMDGPU::SGPR_128RegClass);  in SITargetLowering()
169     addRegisterClass(MVT::v8f16, &AMDGPU::SGPR_128RegClass);  in SITargetLowering()
170     addRegisterClass(MVT::v8bf16, &AMDGPU::SGPR_128RegClass);  in SITargetLowering()
171     addRegisterClass(MVT::v16i16, &AMDGPU::SGPR_256RegClass);  in SITargetLowering()
172     addRegisterClass(MVT::v16f16, &AMDGPU::SGPR_256RegClass);  in SITargetLowering()
173     addRegisterClass(MVT::v16bf16, &AMDGPU::SGPR_256RegClass);  in SITargetLowering()
174     addRegisterClass(MVT::v32i16, &AMDGPU::SGPR_512RegClass);  in SITargetLowering()
175     addRegisterClass(MVT::v32f16, &AMDGPU::SGPR_512RegClass);  in SITargetLowering()
176     addRegisterClass(MVT::v32bf16, &AMDGPU::SGPR_512RegClass);  in SITargetLowering()
179   addRegisterClass(MVT::v32i32, &AMDGPU::VReg_1024RegClass);  in SITargetLowering()
180   addRegisterClass(MVT::v32f32, TRI->getVGPRClassForBitWidth(1024));  in SITargetLowering()