Lines Matching refs:DCI
6859 DAGCombinerInfo DCI(DAG, AfterLegalizeVectorOps, true, nullptr); in lowerEXTRACT_VECTOR_ELT() local
6865 if (SDValue Combined = performExtractVectorEltCombine(Op.getNode(), DCI)) in lowerEXTRACT_VECTOR_ELT()
9985 SDValue SITargetLowering::widenLoad(LoadSDNode *Ld, DAGCombinerInfo &DCI) const { in widenLoad()
9986 SelectionDAG &DAG = DCI.DAG; in widenLoad()
10001 if ((MemVT.isSimple() && !DCI.isAfterLegalizeDAG()) || in widenLoad()
10039 DCI.AddToWorklist(Cvt.getNode()); in widenLoad()
10044 DCI.AddToWorklist(Cvt.getNode()); in widenLoad()
11020 DAGCombinerInfo &DCI) const { in performUCharToFloatCombine()
11026 SelectionDAG &DAG = DCI.DAG; in performUCharToFloatCombine()
11036 if (DCI.isAfterLegalizeDAG() && SrcVT == MVT::i32) { in performUCharToFloatCombine()
11039 DCI.AddToWorklist(Cvt.getNode()); in performUCharToFloatCombine()
11054 DAGCombinerInfo &DCI) const { in performFCopySignCombine()
11057 SelectionDAG &DAG = DCI.DAG; in performFCopySignCombine()
11116 DAGCombinerInfo &DCI) const { in performSHLPtrCombine()
11134 SelectionDAG &DAG = DCI.DAG; in performSHLPtrCombine()
11143 Type *Ty = MemVT.getTypeForEVT(*DCI.DAG.getContext()); in performSHLPtrCombine()
11148 if (!isLegalAddressingMode(DCI.DAG.getDataLayout(), AM, Ty, AddrSpace)) in performSHLPtrCombine()
11180 DAGCombinerInfo &DCI) const { in performMemSDNodeCombine()
11181 SelectionDAG &DAG = DCI.DAG; in performMemSDNodeCombine()
11190 N->getMemoryVT(), DCI); in performMemSDNodeCombine()
11214 DAGCombinerInfo &DCI, in splitBinaryBitConstantOp() argument
11229 return splitBinaryBitConstantOpImpl(DCI, SL, Opc, LHS, ValLo, ValHi); in splitBinaryBitConstantOp()
11316 DAGCombinerInfo &DCI) const { in performAndCombine()
11317 if (DCI.isBeforeLegalize()) in performAndCombine()
11320 SelectionDAG &DAG = DCI.DAG; in performAndCombine()
11329 = splitBinaryBitConstantOp(DCI, SDLoc(N), ISD::AND, LHS, CRHS)) in performAndCombine()
11915 static SDValue matchPERM(SDNode *N, TargetLowering::DAGCombinerInfo &DCI) { in matchPERM() argument
11916 SelectionDAG &DAG = DCI.DAG; in matchPERM()
12005 DAGCombinerInfo &DCI) const { in performOrCombine()
12006 SelectionDAG &DAG = DCI.DAG; in performOrCombine()
12117 if (SDValue Perm = matchPERM(N, DCI)) in performOrCombine()
12122 if (VT != MVT::i64 || DCI.isBeforeLegalizeOps()) in performOrCombine()
12143 DCI.AddToWorklist(LowOr.getNode()); in performOrCombine()
12144 DCI.AddToWorklist(HiBits.getNode()); in performOrCombine()
12155 = splitBinaryBitConstantOp(DCI, SDLoc(N), ISD::OR, in performOrCombine()
12164 DAGCombinerInfo &DCI) const { in performXorCombine()
12165 if (SDValue RV = reassociateScalarOps(N, DCI.DAG)) in performXorCombine()
12172 SelectionDAG &DAG = DCI.DAG; in performXorCombine()
12177 = splitBinaryBitConstantOp(DCI, SDLoc(N), ISD::XOR, LHS, CRHS)) in performXorCombine()
12206 DAGCombinerInfo &DCI) const { in performZeroExtendCombine()
12208 DCI.getDAGCombineLevel() < AfterLegalizeDAG) in performZeroExtendCombine()
12224 DAGCombinerInfo &DCI) const { in performSignExtendInRegCombine()
12242 SDVTList ResList = DCI.DAG.getVTList(MVT::i32); in performSignExtendInRegCombine()
12249 SDValue BufferLoad = DCI.DAG.getMemIntrinsicNode( in performSignExtendInRegCombine()
12251 SDValue LoadVal = DCI.DAG.getNode(ISD::TRUNCATE, DL, VT, BufferLoad); in performSignExtendInRegCombine()
12270 SDVTList ResList = DCI.DAG.getVTList(MVT::i32, in performSignExtendInRegCombine()
12274 SDValue BufferLoadSignExt = DCI.DAG.getMemIntrinsicNode(Opc, SDLoc(N), in performSignExtendInRegCombine()
12278 return DCI.DAG.getMergeValues({BufferLoadSignExt, in performSignExtendInRegCombine()
12285 DAGCombinerInfo &DCI) const { in performClassCombine()
12286 SelectionDAG &DAG = DCI.DAG; in performClassCombine()
12300 DAGCombinerInfo &DCI) const { in performRcpCombine()
12305 return DCI.DAG.getConstantFP( in performRcpCombine()
12312 return DCI.DAG.getNode(AMDGPUISD::RCP_IFLAG, SDLoc(N), VT, N0, in performRcpCombine()
12319 return DCI.DAG.getNode(AMDGPUISD::RSQ, SDLoc(N), VT, in performRcpCombine()
12323 return AMDGPUTargetLowering::performRcpCombine(N, DCI); in performRcpCombine()
12659 DAGCombinerInfo &DCI) const { in performFCanonicalizeCombine()
12660 SelectionDAG &DAG = DCI.DAG; in performFCanonicalizeCombine()
12736 DCI.AddToWorklist(Canon0.getNode()); in performFCanonicalizeCombine()
12874 DAGCombinerInfo &DCI) const { in performMinMaxCombine()
12875 SelectionDAG &DAG = DCI.DAG; in performMinMaxCombine()
12969 DAGCombinerInfo &DCI) const { in performFMed3Combine()
12974 SelectionDAG &DAG = DCI.DAG; in performFMed3Combine()
13013 DAGCombinerInfo &DCI) const { in performCvtPkRTZCombine()
13017 return DCI.DAG.getUNDEF(N->getValueType(0)); in performCvtPkRTZCombine()
13075 SDNode *N, DAGCombinerInfo &DCI) const { in performExtractVectorEltCombine()
13077 SelectionDAG &DAG = DCI.DAG; in performExtractVectorEltCombine()
13100 if (Vec.hasOneUse() && DCI.isBeforeLegalize() && VecEltVT == ResVT) { in performExtractVectorEltCombine()
13128 DCI.AddToWorklist(Elt0.getNode()); in performExtractVectorEltCombine()
13129 DCI.AddToWorklist(Elt1.getNode()); in performExtractVectorEltCombine()
13151 if (!DCI.isBeforeLegalize()) in performExtractVectorEltCombine()
13168 DCI.AddToWorklist(Cast.getNode()); in performExtractVectorEltCombine()
13172 DCI.AddToWorklist(Elt.getNode()); in performExtractVectorEltCombine()
13175 DCI.AddToWorklist(Srl.getNode()); in performExtractVectorEltCombine()
13179 DCI.AddToWorklist(Trunc.getNode()); in performExtractVectorEltCombine()
13194 DAGCombinerInfo &DCI) const { in performInsertVectorEltCombine()
13205 SelectionDAG &DAG = DCI.DAG; in performInsertVectorEltCombine()
13241 DAGCombinerInfo &DCI) const { in performFPRoundCombine()
13254 SelectionDAG &DAG = DCI.DAG; in performFPRoundCombine()
13366 DAGCombinerInfo &DCI) const { in tryFoldToMad64_32()
13369 SelectionDAG &DAG = DCI.DAG; in tryFoldToMad64_32()
13734 DAGCombinerInfo &DCI) const { in performAddCombine()
13735 SelectionDAG &DAG = DCI.DAG; in performAddCombine()
13743 if (SDValue Folded = tryFoldToMad64_32(N, DCI)) in performAddCombine()
13886 if (VT != MVT::i32 || !DCI.isAfterLegalizeDAG()) in performAddCombine()
13924 DAGCombinerInfo &DCI) const { in performSubCombine()
13925 SelectionDAG &DAG = DCI.DAG; in performSubCombine()
13966 DAGCombinerInfo &DCI) const { in performAddCarrySubCarryCombine()
13974 SelectionDAG &DAG = DCI.DAG; in performAddCarrySubCarryCombine()
13990 DAGCombinerInfo &DCI) const { in performFAddCombine()
13991 if (DCI.getDAGCombineLevel() < AfterLegalizeDAG) in performFAddCombine()
13994 SelectionDAG &DAG = DCI.DAG; in performFAddCombine()
14032 DAGCombinerInfo &DCI) const { in performFSubCombine()
14033 if (DCI.getDAGCombineLevel() < AfterLegalizeDAG) in performFSubCombine()
14036 SelectionDAG &DAG = DCI.DAG; in performFSubCombine()
14079 DAGCombinerInfo &DCI) const { in performFDivCombine()
14080 SelectionDAG &DAG = DCI.DAG; in performFDivCombine()
14114 DAGCombinerInfo &DCI) const { in performFMACombine()
14115 SelectionDAG &DAG = DCI.DAG; in performFMACombine()
14189 DAGCombinerInfo &DCI) const { in performSetCCCombine()
14190 SelectionDAG &DAG = DCI.DAG; in performSetCCCombine()
14285 DAGCombinerInfo &DCI) const { in performCvtF32UByteNCombine()
14286 SelectionDAG &DAG = DCI.DAG; in performCvtF32UByteNCombine()
14322 if (TLI.SimplifyDemandedBits(Src, DemandedBits, DCI)) { in performCvtF32UByteNCombine()
14326 DCI.AddToWorklist(N); in performCvtF32UByteNCombine()
14339 DAGCombinerInfo &DCI) const { in performClampCombine()
14344 const MachineFunction &MF = DCI.DAG.getMachineFunction(); in performClampCombine()
14349 return DCI.DAG.getConstantFP(Zero, SDLoc(N), N->getValueType(0)); in performClampCombine()
14354 return DCI.DAG.getConstantFP(One, SDLoc(N), N->getValueType(0)); in performClampCombine()
14361 DAGCombinerInfo &DCI) const { in PerformDAGCombine()
14366 return performAddCombine(N, DCI); in PerformDAGCombine()
14368 return performSubCombine(N, DCI); in PerformDAGCombine()
14371 return performAddCarrySubCarryCombine(N, DCI); in PerformDAGCombine()
14373 return performFAddCombine(N, DCI); in PerformDAGCombine()
14375 return performFSubCombine(N, DCI); in PerformDAGCombine()
14377 return performFDivCombine(N, DCI); in PerformDAGCombine()
14379 return performSetCCCombine(N, DCI); in PerformDAGCombine()
14392 return performMinMaxCombine(N, DCI); in PerformDAGCombine()
14394 return performFMACombine(N, DCI); in PerformDAGCombine()
14396 return performAndCombine(N, DCI); in PerformDAGCombine()
14398 return performOrCombine(N, DCI); in PerformDAGCombine()
14403 return matchPERM(N, DCI); in PerformDAGCombine()
14408 return performXorCombine(N, DCI); in PerformDAGCombine()
14410 return performZeroExtendCombine(N, DCI); in PerformDAGCombine()
14412 return performSignExtendInRegCombine(N , DCI); in PerformDAGCombine()
14414 return performClassCombine(N, DCI); in PerformDAGCombine()
14416 return performFCanonicalizeCombine(N, DCI); in PerformDAGCombine()
14418 return performRcpCombine(N, DCI); in PerformDAGCombine()
14433 return performUCharToFloatCombine(N, DCI); in PerformDAGCombine()
14435 return performFCopySignCombine(N, DCI); in PerformDAGCombine()
14440 return performCvtF32UByteNCombine(N, DCI); in PerformDAGCombine()
14442 return performFMed3Combine(N, DCI); in PerformDAGCombine()
14444 return performCvtPkRTZCombine(N, DCI); in PerformDAGCombine()
14446 return performClampCombine(N, DCI); in PerformDAGCombine()
14448 SelectionDAG &DAG = DCI.DAG; in PerformDAGCombine()
14466 return performExtractVectorEltCombine(N, DCI); in PerformDAGCombine()
14468 return performInsertVectorEltCombine(N, DCI); in PerformDAGCombine()
14470 return performFPRoundCombine(N, DCI); in PerformDAGCombine()
14472 if (SDValue Widened = widenLoad(cast<LoadSDNode>(N), DCI)) in PerformDAGCombine()
14477 if (!DCI.isBeforeLegalize()) { in PerformDAGCombine()
14479 return performMemSDNodeCombine(MemNode, DCI); in PerformDAGCombine()
14486 return AMDGPUTargetLowering::PerformDAGCombine(N, DCI); in PerformDAGCombine()