Lines Matching refs:ComputeLoop

4634     auto [ComputeLoop, ComputeEnd] = splitBlockForLoop(MI, BB, true);  in lowerWaveReduce()
4661     BuildMI(BB, I, DL, TII->get(AMDGPU::S_BRANCH)).addMBB(ComputeLoop);  in lowerWaveReduce()
4664     I = ComputeLoop->end();  in lowerWaveReduce()
4666         BuildMI(*ComputeLoop, I, DL, TII->get(AMDGPU::PHI), AccumulatorReg)  in lowerWaveReduce()
4670         BuildMI(*ComputeLoop, I, DL, TII->get(AMDGPU::PHI), ActiveBitsReg)  in lowerWaveReduce()
4676     auto FF1 = BuildMI(*ComputeLoop, I, DL, TII->get(SFFOpc), FF1Reg)  in lowerWaveReduce()
4678     auto LaneValue = BuildMI(*ComputeLoop, I, DL,  in lowerWaveReduce()
4682     auto NewAccumulator = BuildMI(*ComputeLoop, I, DL, TII->get(Opc), DstReg)  in lowerWaveReduce()
4690         BuildMI(*ComputeLoop, I, DL, TII->get(BITSETOpc), NewActiveBitsReg)  in lowerWaveReduce()
4696         .addMBB(ComputeLoop);  in lowerWaveReduce()
4698         .addMBB(ComputeLoop);  in lowerWaveReduce()
4702     BuildMI(*ComputeLoop, I, DL, TII->get(CMPOpc))  in lowerWaveReduce()
4705     BuildMI(*ComputeLoop, I, DL, TII->get(AMDGPU::S_CBRANCH_SCC1))  in lowerWaveReduce()
4706         .addMBB(ComputeLoop);  in lowerWaveReduce()